Digital Input, Mono 2 W, Class-D Audio Power Amplifier Data Sheet SSM2529 This unique architecture enables extremely low real-world power FEATURES consumption from digital audio sources with excellent audio Filterless mono, digital input Class-D amplifier performance. The SSM2529 is ideal for power sensitive applications, 2 I C control interface such as mobile phones and portable media players, where system Serial digital audio interface supports common formats noise can the corrupt small analog signals that are sent to an 2 (I S, PCM, LJ, RJ, TDM1-16, PDM) analog input audio amplifier. Supports wide range of sample rates: 8.0 kHz to 96.0 kHz MCLK and BCLK can be provided by built-in phase-locked Using the SSM2529, audio data can be transmitted to the amplifier loop (PLL) over a standard digital audio serial interface, thereby significantly Supports single power supply mode DVDD can be provided reducing the effect of noise sources such as GSM interference or by built-in low dropout (LDO) regulator other digital signals on the transmitted audio. The closed-loop 2.5 V to 5.5 V SPKVDD operating supply voltage digital input design retains the benefits of an all-digital amplifier, yet 1.08 V to 1.98 V DVDD operating supply voltage enables very good PSRR and audio performance. The three-level, 2 Support off-chip volume control without I C - Class-D modulator is designed to provide the least amount of 2.4 W into 4 a nd 1.4 W into 8 at 5 V supply with <1% THD + N EMI, the lowest quiescent power dissipation, and the highest Available in a 16-ball, 1.92 mm 1.94 mm, 0.4 mm pitch WLCSP audio efficiency without sacrificing audio quality. Efficiency 95% at full scale into 8 The audio input is provided via a serial audio interface that can be Signal-to-noise ratio (SNR): 103 dB, A-weighted 2 programmed to accept all common audio formats, including I S, Power supply rejection ratio (PSRR): >80 dB at 217 Hz 2 TDM, and PDM. Control of the IC is provided via an I C control Digital volume control: 70 dB to +24 dB in 0.375 dB steps 2 interface. An alternative to I C control is standalone operation Ultralow idle current mode, which allows several settings that are adjusted by off-chip Autosample rate detection external resistors. The SSM2529 can accept a variety of input MCLK Pop-and-click suppression frequencies and can use BCLK as the clock source in some Short-circuit and thermal protection with programmable configurations. An integrated PLL can also provide the device autorecovery master clock. Supports smart power-down when no input signal is detected The integrated DSP includes soft digital volume control circuits a Power-on reset and UVLO voltage monitoring de-emphasis, high-pass filter a seven-band programmable equalizer Selectable ultralow EMI emission mode and a programmable digital dynamic range compressor. In addition, Supports SPKVDD voltage monitor the part includes a feedforward speaker temperature prediction Digital audio processing module to protect the loudspeaker. 7-band programmable equalizer Programmable dynamic range compression (DRC) with The SSM2529 supports single-supply mode, where DVDD is noise gate, expander, compressor, and limiter provided by the on-chip LDO regulator, eliminating the need for an external digital core supply. APPLICATIONS The digital interface is very flexible and convenient. It can offer a Mobile phones better system solution for other products whose sole audio source Portable media players is digital, such as wireless speakers, laptop PCs, portable digital Laptop PCs televisions, and navigation systems. Wireless speakers Portable gaming The SSM2529 is specified over the industrial temperature range of Navigation systems 40C to +85C. It has built-in thermal shutdown and output short- circuit protection. It is available in a 16-ball, 1.92 mm 1.94 mm GENERAL DESCRIPTION wafer level chip scale package (WLCSP). The SSM2529 is a digital input, Class-D power amplifier that combines a digital-to-analog converter (DAC), a low power audio specific digital signal processor, and a sigma-delta (-) Class-D modulator. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2012 Analog Devices, Inc. All rights reserved. SSM2529 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Audio Interface and Sample Rate Control (SAI FMT1) Register ........................................................................................ 28 Applications ....................................................................................... 1 Serial Audio Interface Control (SAI FMT2) Register .......... 29 General Description ......................................................................... 1 Channel Mapping Control Register ......................................... 30 Revision History ............................................................................... 3 Volume Control Before FDSP (VOL BF FDSP) Register ... 31 Functional Block Diagram .............................................................. 4 Volume Control After FDSP (VOL AF FDSP) Register ..... 31 Specifications ..................................................................................... 5 Volume and Mute Control Register ......................................... 31 Performance Specifications ......................................................... 5 DPLL CTRL Register ................................................................ 32 Power Supply Requirements ....................................................... 6 APLL CTRL1 Register .............................................................. 32 Digital Input/Output .................................................................... 6 APLL CTRL2 Register .............................................................. 32 Digital Interpolation Filter .......................................................... 6 APLL CTRL3 Register .............................................................. 32 Digital Timing ............................................................................... 6 APLL CTRL4 Register .............................................................. 32 Absolute Maximum Ratings ............................................................ 8 APLL CTRL5 Register .............................................................. 33 Thermal Resistance ...................................................................... 8 APLL CTRL6 Register .............................................................. 33 ESD Caution .................................................................................. 8 FAULT CTRL1 Register ........................................................... 34 Pin Configuration and Function Descriptions ............................. 9 FAULT CTRL2 Register ........................................................... 34 Typical Performance Characteristics ........................................... 10 DEEMP CTRL Register ............................................................ 34 Theory of Operation ...................................................................... 14 HPF CTRL Register .................................................................. 35 Overview ...................................................................................... 14 EQ1 COEF0 HI Register ......................................................... 35 Master Clock ............................................................................... 14 EQ1 COEF0 LO Register ........................................................ 35 Internal Clock Generator .......................................................... 14 EQ1 COEF1 HI Register ......................................................... 35 Digital Input Serial Audio Interface ......................................... 14 EQ1 COEF1 LO Register ........................................................ 35 PDM Mode Setup and Control ................................................. 15 EQ1 COEF2 HI Register ......................................................... 36 High-Pass Filter .......................................................................... 15 EQ1 COEF2 LO Register ........................................................ 36 Fully Programmable Seven-Band Equalizer ............................... 15 EQ1 COEF3 HI Register ......................................................... 36 Dynamic Range Control ............................................................ 18 EQ1 COEF3 LO Register ........................................................ 36 DRC Mode Control .................................................................... 18 EQ1 COEF4 HI Register ......................................................... 36 Gain Ripple Remove .................................................................. 21 EQ1 COEF4 LO Register ........................................................ 36 Speaker Protection ..................................................................... 21 EQ2 COEF0 HI Register ......................................................... 36 Power Supplies ............................................................................ 21 EQ2 COEF0 LO Register ........................................................ 36 Power Control ............................................................................. 21 EQ2 COEF1 HI Register ......................................................... 36 Power-On Reset/Voltage Supervisor ........................................ 22 EQ2 COEF1 LO Register ........................................................ 36 Standalone Mode ........................................................................ 22 2 EQ2 COEF2 HI Register ......................................................... 37 I C Port......................................................................................... 22 EQ2 COEF2 LO Register ........................................................ 37 Register Summary .......................................................................... 24 EQ2 COEF3 HI Register ......................................................... 37 Register Details ............................................................................... 27 EQ2 COEF3 LO Register ........................................................ 37 Software Reset and Master Software Power-Down Control (PWR CTRL) Register .............................................................. 27 EQ2 COEF4 HI Register ......................................................... 37 MCLK Ratio and Frequency ..................................................... 27 EQ2 COEF4 LO Register ........................................................ 37 Edge Speed and Clocking Control (SYS CTRL) Register .... 28 EQ3 COEF0 HI Register ......................................................... 37 EQ3 COEF0 LO Register ........................................................ 37 Rev. 0 Page 2 of 52