Mono 2.9 W Class-D Audio Amplifier with Digital Current and Voltage Output Data Sheet SSM4321 The SSM4321 features a high efficiency, low noise modulation FEATURES scheme that requires no external LC output filters. The modulation Filterless Class-D amplifier with spread-spectrum scheme provides high efficiency even at low output power. The - modulation SSM4321 operates with 89% efficiency at 1.4 W into 8 from Digitized output of output voltage, output current, a 5.0 V supply with an SNR of >100 dB. and PVDD supply voltage 72 dB signal-to-noise ratio (SNR) on output current sensing The SSM4321 includes circuitry to sense output current, output and 77 dB SNR on output voltage sensing voltage, and the PVDD supply voltage. Current sense is performed 2 TDM or multichip I S slave output interface using an external sense resistor that is connected between an Up to 4 chips supported on a single bus output pin and the load. The output current and voltage are sent 8 kHz to 48 kHz operation to ADCs with 16-bit resolution the PVDD supply voltage is sent 2 I S/left justified slave output interface to an ADC with 8-bit resolution. 1 or 2 chips supported on a single bus 2 The outputs of these ADCs are available on the TDM or I S 8 kHz to 48 kHz operation output serial port. The SLOT pin is used to determine which of PDM output interface operates from 1 MHz to 6.144 MHz four possible output slots is used on the TDM interface. A stereo 2.2 W into 4 load and 1.4 W into 8 load at 5.0 V supply 2 I S interface can be selected by reversing the pin connections for with <1% total harmonic distortion plus noise (THD + N) BCLK and FSYNC. Also, a direct PDM bit stream of voltage and 89% efficiency at 5.0 V, 1.4 W into 8 + 0.2 R speaker SENSE current data can be selected via the SLOT pin. >100 dB signal-to-noise ratio (SNR) Spread-spectrum pulse density modulation (PDM) is used to High PSRR at 217 Hz: 86 dB provide lower EMI-radiated emissions compared with other Amplifier supply operation from 2.5 V to 5.5 V Class-D architectures. The inherent randomized nature of Input/output supply operation from 1.42 V to 3.6 V spread-spectrum PDM eliminates the clock intermodulation Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps (beating effect) of several amplifiers in close proximity. with fixed input impedance of 80 k <1 A shutdown current The SSM4321 produces ultralow EMI emissions that significantly Smart power-down with loss of BCLK reduce the radiated emissions at the Class-D outputs, particularly Short-circuit and thermal protection with autorecovery above 100 MHz. The ultralow EMI emissions of the SSM4321 are Available in a 16-ball, 0.4 mm pitch, 1.74 mm 1.74 mm WLCSP also helpful for antenna and RF sensitivity problems. Pop-and-click suppression The device includes a highly flexible gain select pin that requires APPLICATIONS only one series resistor to select a gain setting of 0 dB, 3 dB, 6 dB, 9 dB, or 12 dB. Input impedance is fixed at 80 k, independent Mobile phones of the selected gain. MP3 players Portable electronics The SSM4321 has a shutdown mode with a typical shutdown current of <1 A. Shutdown is enabled by removing the BCLK GENERAL DESCRIPTION input. A clock must be present on the BCLK pin for the part The SSM4321 is a fully integrated, high efficiency, Class-D to operate. audio amplifier with digitized output of output voltage, output The device also includes pop-and-click suppression circuitry, current, and the PVDD supply voltage. It is designed to maximize which minimizes voltage glitches at the output during turn-on performance for mobile phone applications. The application circuit and turn-off, reducing audible noise on activation and deactivation. requires a minimum of external components and operates from a 2.5 V to 5.5 V supply for the amplifier and a 1.42 V to 3.6 V The SSM4321 is specified over the industrial temperature range supply for input/output. The SSM4321 is capable of delivering of 40 C to +85 C. It has built-in thermal shutdown and output 2.2 W of continuous output power with <1% THD + N driving short-circuit protection. It is available in a halide-free, 16-ball, a 4 load from a 5.0 V supply with a 0.1 V/I sense resistor. 0.4 mm pitch, 1.74 mm 1.74 mm wafer level chip scale package (WLCSP). Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SSM4321 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Current Sensing ............................................................ 15 Applications ....................................................................................... 1 Output Voltage Sensing ............................................................. 15 General Description ......................................................................... 1 PVDD Sensing ............................................................................ 15 Revision History ............................................................................... 2 Serial Data Input/Output............................................................... 16 Functional Block Diagram .............................................................. 3 TDM Operating Mode .............................................................. 16 2 Specifications ..................................................................................... 4 I S and Left Justified Operating Mode .................................... 16 2 Digital Input/Output Specifications........................................... 5 Multichip I S Operating Mode ................................................. 17 Absolute Maximum Ratings ............................................................ 6 PDM Output Mode .................................................................... 17 Thermal Resistance ...................................................................... 6 Timing Diagrams, TDM Mode ................................................ 18 2 ESD Caution .................................................................................. 6 Timing Diagrams, I S and Left Justified Modes ..................... 18 2 Pin Configuration and Function Descriptions ............................. 7 Timing Diagrams, Multichip I S Mode ................................... 19 Typical Performance Characteristics ............................................. 8 Timing Diagrams, PDM Mode ................................................. 20 Theory of Operation ...................................................................... 14 Applications Information .............................................................. 21 Overview ...................................................................................... 14 Layout .......................................................................................... 21 Power-Down Operation ............................................................ 14 Input Capacitor Selection .......................................................... 21 Gain Selection ............................................................................. 14 Power Supply Decoupling ......................................................... 21 Pop-and-Click Suppression ....................................................... 14 Outline Dimensions ....................................................................... 22 Output Modulation Description .............................................. 14 Ordering Guide .......................................................................... 22 EMI Noise .................................................................................... 15 REVISION HISTORY 10/12Revision 0: Initial Version Rev. 0 Page 2 of 24