4 W, GaAs, pHEMT, MMIC Power Amplifier, 5.5 GHz to 8.5 GHz Data Sheet HMC1121 FEATURES FUNCTIONAL BLOCK DIAGRAM High saturated output power (P ): 36.5 dBm at 30% power SAT added efficiency (PAE) High output third-order intercept (IP3): 44 dBm typical High gain: 28 dB typical NIC 1 30 NIC NIC 2 29 NIC High output power for 1 dB compression (P1dB): 36 dBm typical HMC1121 NIC 3 28 NIC Total supply current: 2200 mA at 7 V NIC 4 27 NIC 2 40-lead, 6 mm 6 mm LFCSP package: 36 mm RFIN 5 26 RFOUT NIC 6 25 NIC APPLICATIONS NIC V 7 24 DET V NIC 8 23 REF Point to point radios NIC 9 22 NIC Point to multipoint radios NIC 10 21 NIC Very small aperture terminals (VSATs) and satellite communications (SATCOMs) PACKAGE BASE Military electronic warfare (EW) and electronic counter measures (ECM) Figure 1. The HMC1121 exhibits excellent linearity and it is optimized GENERAL DESCRIPTION for high capacity, point to point and point to multipoint radio The HMC1121 is a three-stage, gallium arsenide (GaAs), systems. The amplifier configuration and high gain make it an pseudomorphic high electron mobility transfer (pHEMT), excellent candidate for last stage signal amplification preceding monolithic microwave integrated circuit (MMIC), 4 W power the antenna. amplifier with an integrated temperature compensated on-chip Ideal for supporting higher volume applications, the HMC1121 power detector that operates between 5.5 GHz and 8.5 GHz. is provided in a 40-lead LFCSP package. The HMC1121 provides 28 dB of gain, 44 dBm output IP3, and 36.5 dBm of saturated output power at 30% PAE from a 7 V power supply. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. NIC NIC NIC NIC NIC NIC V V GG3 GG1 V V DD3 DD1 NIC NIC V V GG4 GG2 NIC NIC V V DD4 DD2 NIC NIC 13529-001 11 40 12 39 13 38 14 37 15 36 16 35 17 34 18 33 19 32 20 31HMC1121 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 12 General Description ......................................................................... 1 Recommended Bias Sequence .................................................. 12 Revision History ............................................................................... 2 Typical Application Circuit ....................................................... 12 Specifications ..................................................................................... 3 Evaluation Board ............................................................................ 13 Electrical Specifications ............................................................... 3 Bill of Materials ........................................................................... 13 Absolute Maximum Ratings ............................................................ 4 Evaluation Board Schematic ..................................................... 14 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 15 Interface Schematics..................................................................... 6 REVISION HISTORY 10/2017Rev. 0 to Rev. A Changes to Figure 32 ...................................................................... 11 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 7/2016Revision 0: Initial Version Rev. A Page 2 of 15