High Speed Converter Evaluation Platform HSC-ADC-EVALC FEATURES PRODUCT HIGHLIGHTS Xilinx Virtex-4 FPGA-based buffer memory board 1. Easy to Set Up. Connect the included power supply along Used for capturing digital data from high speed ADC with the CLK and AIN signal sources to the two evaluation evaluation boards to simplify evaluation boards. Then connect to the PC via the USB port and 64 kB FIFO depth evaluate the performance instantly. Parallel input at 644 MSPS SDR and 800 MSPS DDR 2. USB Port Connection to PC. PC interface is via a USB 2.0 Supports 1.8 V, 2.5 V, and 3.3 V CMOS and LVDS interfaces connection (1.1 compatible) to the PC. A USB cable is Supports multiple ADC channels up to 18 bits provided in the kit. Measures performance with VisualAnalog 3. 64 kB FIFO. The on-board FPGA contains an integrated Real-time FFT and time domain analysis FIFO to store data captured from the ADC for subsequent Analyzes SNR, SINAD, SFDR, and harmonics processing. Simple USB port interface (2.0) 4. Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on Supports ADCs with serial port interfaces (SPI) Each Channel. Multichannel ADCs with encode rates up FPGA reconfigurable via JTAG, on-board EPROM, or USB to 644 MSPS SDR and 800 MSPS DDR can be used with On-board regulator circuit speeds setup the ADC capture board. 5 V, 3 A switching power supply included 5. Supports ADCs with Serial Port Interface or SPI. Some Compatible with Windows 98 (2nd edition), Windows 2000, ADCs include a feature set that can be changed via the Windows ME, and Windows XP SPI. The ADC capture board supports these SPI-driven features through the existing USB connection to the EQUIPMENT NEEDED computer without additional cabling needed. Analog signal source and antialiasing filter 6. VisualAnalog. VisualAnalog supports the HSC-ADC- Low jitter clock source EVALC hardware platform as well as enabling virtual ADC High speed ADC evaluation board and ADC data sheet evaluation using ADIsimADC, Analog Devices proprietary PC running Windows 98 (2nd edition), Windows 2000, behavioral modeling technology. This allows rapid compari- Windows ME, or Windows XP son between multiple ADCs, with or without hardware Latest version of VisualAnalog USB 2.0 port recommended (USB 1.1 compatible) evaluation boards. For more information, see AN-737 at www.analog.com/VisualAnalog. FUNCTIONAL BLOCK DIAGRAM ON-BOARD POWER HSC-ADC-EVALC VOLTAGE USB CONNECTOR REGULATORS SINGLE OR MULTICHANNEL FPGA LED2 LED1 UPLOAD CAPTURE HIGH SPEED ADC CONFIGURATION MODE EVALUATION BOARD PORTB DATA(16) DATA BUS 2(18) PORTD n FILTERED J3* J6 FIFO ANALOG CLKA(2) USB CONTROL(9) INPUT FPGA CONTROLLER ADC USB CONNECTOR DATA BUS 1(18) PORTC n J2* PORTE CLKB(2) STANDARD PORTA EXT SYNC1 USB 2.0 FPGA CLOCK USB DONE ONBOARD CONFIG CIRCUIT EXT SYNC2 VOLTAGE J4 PROM REGULATORS FPGA CONFIG POWER PROM CONNECTOR FPGA GPIO(8) SPI(7) J1* SPI RECONFIG USB DIRECT(5) J10 *DATA CONVERTER I/O CONNECTORS JTAG CONNECTOR CLOCK INPUT Figure 1. Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards as supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. from its use. Analog Devices reserves the right to change devices or specifications at any time Tel: 781.329.4700 www.analog.com without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. Fax: 781.461.3113 2007 Analog Devices, Inc. All rights reserved. LOGIC 06676-001HSC-ADC-EVALC TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................8 Equipment Needed........................................................................... 1 Configuration ................................................................................8 Product Highlights ........................................................................... 1 Input Circuitry...............................................................................8 Functional Block Diagram .............................................................. 1 Data Capture..................................................................................8 Revision History ............................................................................... 2 Code Description ..........................................................................8 Product Description......................................................................... 3 FPGA Configuration and Customization..................................8 Evaluation Board Description......................................................... 3 Evaluation Board Schematics and Artwork...................................9 Evaluation Board Hardware............................................................ 4 HSC-ADC-EVALC Schematics...................................................9 HSC-ADC-EVALC ADC Capture Board Easy Start ............... 4 PCB Layout ................................................................................. 23 Power Supplies .............................................................................. 4 I/O ConnectorJ1, J2, and J3 Pin Mapping .......................... 24 Connection and Setup ................................................................. 4 Ordering Information.................................................................... 28 Jumpers .......................................................................................... 5 Bill of Materials (RoHS Compliant) ........................................ 28 HSC-ADC-EVALC ADC Capture Board Features.................. 6 Ordering Guide .......................................................................... 30 HSC-ADC-EVALC Supported ADC Evaluation Boards........ 7 ESD Caution................................................................................ 30 REVISION HISTORY 4/07Revision 0: Initial Version Rev. 0 Page 2 of 32