Evaluation Board User Guide UG-173 One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com High Speed ADC USB FIFO Evaluation Kit (HSC-ADC-EVALB-DCZ) FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data used with high speed ADC evaluation boards to simplify evaluation 32 kB FIFO depth at 133 MSPS (upgradable) STANDARD Measures performance with ADC Analyzer USB 2.0 Real-time FFT and time domain analysis Analyze SNR, SINAD, SFDR, and harmonics Simple USB port interface (2.0) Supporting ADCs with serial port interfaces (SPI) On-board regulator circuit, no power supply required 6 V, 2 A SINGLE OR DUAL switching power supply included HIGH-SPEED ADC EVALUATION BOARD Compatible with Windows 98 (2nd ed.), Windows 2000, HSC-ADC-EVALB-DCZ Windows ME, and Windows XP CHB FIFO, PS PS REG n 32k, 133MHz FILTERED +3.0V ANALOG REG EQUIPMENT NEEDED INPUT TIMING ADC CIRCUIT Analog signal source and antialiasing filter USB CTLR Low jitter clock source CHA FIFO, n High speed ADC evaluation board and ADC data sheet 32k, CLOCK 133MHz CIRCUIT PC running Windows 98 (2nd ed.), Windows 2000, Windows ME, SPI SPI or Windows XP Latest version of ADC Analyzer CLOCK INPUT 120-PIN CONNECTOR USB 2.0 (USB 1.1-compatible) port recommended Figure 1. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. Easy to Set Up. Connect the included power supply and signal sources to the two evaluation boards. Then connect The high speed ADC FIFO evaluation kit includes the latest to the PC and instantly evaluate the performance. version of ADC Analyzer and a buffer memory board to capture blocks of digital data from the Analog Devices, Inc., high speed 2. ADIsimADC. ADC Analyzer supports virtual ADC analog-to-digital converter (ADC) evaluation boards. The FIFO evaluation using Analog Devices proprietary behavioral board is connected to the PC through a USB port and is used with modeling technology. This allows rapid comparison between ADC Analyzer to quickly evaluate the performance of high speed multiple ADCs, with or without hardware evaluation boards. ADCs. Users can view an FFT for a specific analog input and For more information, see the AN-737 at www.analog.com. encode rate to analyze SNR, SINAD, SFDR, and harmonic 3. USB Port Connection to PC. The PC interface is a USB 2.0 information. (1.1-compatible) connection. A USB cable is provided in the kit. 4. FIFO of 32 kB. The FIFO stores data from the ADC for processing. The evaluation kit is easy to set up. Additional equipment needed A pin-compatible FIFO family is used for easy upgrading. includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected 5. Up to 133 MSPS Encode Rate on Each Channel. Single-channel and powered, the evaluation is enabled instantly on the PC. ADCs with encode rates of up to 133 MSPS can be used with the FIFO board. Multichannel and demultiplexed output ADCs can The HSC-ADC-EVALB-DCZ can be used with single and multi- also be used with the FIFO board with clock rates up to 266 MSPS. channel ADCs and converters with demultiplexed digital outputs. 6. Supports ADC with Serial Port Interface (SPI). Some ADCs include a feature set that can be changed via the SPI. The FIFO supports these features through the existing USB connection to the computer without requiring additional cabling. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B Page 1 of 24 LOGIC 05870-001UG-173 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Connecting to the HSC-ADC-AD922xFFA or HSC-ADC- AD9283FFA Adapter Boards .......................................................8 Equipment Needed ........................................................................... 1 Connecting to the HSC-ADC-DEMUXZ Adapter Board .......8 General Description ......................................................................... 1 Connecting ADC Evaluation Boards with Double Row Functional Block Diagram .............................................................. 1 Connectors .....................................................................................8 Product Highlights ........................................................................... 1 Upgrading FIFO Memory ............................................................8 Revision History ............................................................................... 2 Jumpers ...............................................................................................9 Quick Start Guide: FIFO Evaluation Board .................................. 3 Default Settings ..............................................................................9 Requirements ................................................................................ 3 Evaluation Board ............................................................................ 11 Quick Start Steps .......................................................................... 3 Power Supplies ............................................................................ 11 Quick Start Guide: Virtual Evaluation Using ADIsimADC ....... 4 Connection and Setup ............................................................... 11 Requirements ................................................................................ 4 FIFO Schematics and PCB Layout ............................................... 12 Quick Start Steps .......................................................................... 4 Pin Definitions/Assignments .................................................... 12 FIFO 4.1 Data Capture Board Features ......................................... 5 Schematics ................................................................................... 13 FIFO 4.1 Supported ADC Evaluation Boards .......................... 6 PCB Layout ................................................................................. 20 Theory of Operation ........................................................................ 7 Ordering Information .................................................................... 22 Clocking Description ................................................................... 7 Bill of Materials ........................................................................... 22 SPI Description ............................................................................. 7 Related Links ............................................................................... 24 Clocking with Interleaved Data .................................................. 8 Connecting to the HSC-ADC-FIFO5-INTZ ............................ 8 REVISION HISTORY 7/10Rev. A to Rev. B Added the Connecting to the HSC-ADC-AD922xFFA or Document Title Changed from HSC-ADC-EVALB to HSC-ADC-AD9283FFA Adapter Boards Section ........................ 8 UG-173 ................................................................................. Univers al Changes to the Connecting to the HSC-ADC-DEMUX Adapter Changed Connecting to the HSC-ADC-FPGA-8Z Section to Board Section ..................................................................................... 8 Connecting to the HSC-ADC-FIFO5-INTZ Section .................. 8 Added the Connecting ADC Evaluation Boards with Double Changes to Connecting to the HSC-ADC-FIFO5-INTZ Row Connectors Section .................................................................. 8 Section ................................................................................................ 8 Added Figure 4 and Figure 5 ............................................................ 8 Changed Connecting to the HSC-ADC-DEMUX Adapter Added Figure 7 ................................................................................ 12 Board Section to Connecting to the HSC-ADC-DEMUXZ Changes to Schematics .................................................................. 13 Adapter Board Section ..................................................................... 8 Changes to Bill of Materials .......................................................... 22 Changes to Related Links Section ................................................ 24 Changes to Ordering Guide .......................................................... 24 7/07Rev. 0 to Rev. A 2/06Revision 0: Initial Version Deleted HSC-ADC-EVALB-SC Universal Changes to Table 1 ............................................................................ 8 Rev. B Page 2 of 24