LTC4291-1/LTC4292 4-Port IEEE 802.3bt PoE PSE Controller FEATURES DESCRIPTION n Four PSE Ports The LTC 4291-1/LTC4292 chipset is a 4-port power n Two Power Channels per Port sourcing equipment (PSE) controller designed for use in n Fully Compliant IEEE 802.3bt Type 3 and 4 PSE IEEE 802.3bt Type 3 and 4 compliant Power over Ethernet n Compliant Support for Type 1, 2, 3, and 4 PDs (PoE) systems. The LTC4291-1/LTC4292 is designed to n Low Power Path Dissipation per Channel power compliant 802.3af, 802.3at, and 802.3bt PDs. The n 150m Sense Resistance LTC4291-1/LTC4292 chipset delivers lowest-in-indus- n 30m or Lower MOSFET R try heat dissipation by utilizing low R external DS(ON) DS(ON) n Chipset Provides Electrical Isolation MOSFETs and 0.15 sense resistance per power channel. n Eliminates Optos and Isolated 3.3V Supply Atransformer-isolated communication protocol replaces n Very High Reliability Multipoint PD Detection expensive opto-couplers and complex isolated 3.3V sup- n Connection Check Distinguishes Single- ply, resulting in significant BOM cost savings. Signature and Dual-Signature PDs Advanced power management features include per-port n Continuous, Dedicated Per-Port Power and Current 14-bit current monitoring, programmable current limit, Monitoring and versatile fast shutdown of preselected ports. Advanced n Per-Port Power Policing power management host software is available under a no- 2 n 1MHz I C Compatible Serial Control Interface cost license. PD detection uses a proprietary multipoint 2 n Pin or I C Programmable PD Power Up to 71.3W detection mechanism ensuring excellent immunity from n Available in a 40-Lead 6mm 6mm (LTC4292) and false PD identification. Autoclass and 5-event physical 24-Lead 4mm 4mm (LTC4291-1) QFN Packages classification are supported. The LTC4291-1/LTC4292 2 includes an I C serial interface operable up to 1MHz. The 2 APPLICATIONS LTC4291-1/LTC4292 is pin or I C programmable to nego- tiate PD delivered power up to 71.3W. n PoE PSE Switches/Routers All registered trademarks and trademarks are the property of their respective owners. n PoE PSE Midspans TYPICAL APPLICATION AGNDP 10 0.1F 3.3V 1 1F >47F 100V AGNDP TX1 0.22F V EE S1B 100V 2 V AGNDP DD GP0 PWRMD0 OUTnA ISOLATION GP1 PWRMD1 3 S1B CPD CPA GATEnA 4PVALID TX2 0.15 100 100 AUTO V EE 6 2 3.3V V SENSEnA VSSKn (NO I C EE RESET ISOLATION 100 100 4 REQUIRED) MSD AGNDP CND CNA TX3 0.22F DPD DPA LTC4291-1 LTC4292 S1B INT 100V 5 100 100 SCL OUTnB 3.3V V EE SDAIN 7 100 100 SDAOUT S1B GATEnB DND DNA TX4 0.15 AD0 V EE 1F 0.22F AD1 8 SENSEnB VSSKn AD2 CAP1 CAP2 2nF 1000BASE-T RJ45 AD3 DGND 2kV V VSSKn 42911 TA01a EE 0.22F, 100V (1 OF 4 PORTS) AGNDP V 0.15 EE VSSKn Rev 0 1 Document Feedback For more information www.analog.comLTC4291-1/LTC4292 ABSOLUTE MAXIMUM RATINGS (Notes 1, 4) (Note 1) LTC4292 LTC4291-1 Supply Voltages Supply Voltages AGNDP V ......................................... 0.3V to 80V V DGND ......................................... 0.3V to 3.6V EE DD VSSK12, VSSK34 (Note 7) ... V 0.3V to V + 0.3V Digital Pins EE EE Digital Pins SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO, PWRMD0, PWRMD1 ........ V 0.3V to CAP2 + 0.3V 4PVALID, GPn .................DGND 0.3V to V + 0.3V EE DD Analog Pins Analog Pins SENSEnM, GATEnM, OUTnM V 0.3V to V + 80V CAP1 (Note 13) ...........................0.3V to DGND + 2V EE EE CAP2 (Note 13) ...................... V 0.3V to V + 5V CPD, CND, DPD, DND ......DGND 0.3V to V + 0.3V EE EE DD CPA, CNA, DPA, DNA ..............V 0.3V to V + 0.3 Operating Ambient Temperature Range EE EE Operating Ambient Temperature Range LTC4291I-1 ..........................................40C to 85C LTC4292I .............................................40C to 85C Junction Temperature (Note 2) ............................ 125C Junction Temperature (Note 2) ............................ 125C Storage Temperature Range .................. 65C to 150C Storage Temperature Range .................. 65C to 150C PIN CONFIGURATION LTC4292 LTC4291-1 TOP VIEW TOP VIEW 40 39 38 37 36 35 34 33 32 31 GATE1A 1 30 GATE4B OUT1A 2 29 OUT4B 24 23 22 21 20 19 GATE1B 3 28 GATE4A AD0 1 18 SCL OUT1B 4 27 OUT4A AD1 SDAIN 2 17 VSSK12 5 41 26 VSSK34 V AD2 3 16 SDAOUT EE 25 CAP2 6 25 AGNDP DGND AD3 4 15 INT GATE2A 7 24 GATE3B DGND 5 14 RESET OUT2A 8 23 OUT3B 4PVALID 6 13 DNC GATE2B 9 22 GATE3A OUT2B 10 21 OUT3A 7 8 9 10 11 12 11 12 13 14 15 16 17 18 19 20 UF PACKAGE 24-LEAD (4mm 4mm) PLASTIC QFN T = 125C, = 4C/W, = 47C/W JMAX JC JA EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB UJ PACKAGE 40-LEAD (6mm 6mm) PLASTIC QFN T = 125C, = 2C/W, = 33C/W JMAX JC JA EXPOSED PAD (PIN 41) IS V , MUST BE SOLDERED TO PCB EE Rev 0 2 For more information www.analog.com PWRMD0 V EE SENSE1A CPA SENSE1B CNA SENSE2A DPA SENSE2B DNA SENSE3A NC SENSE3B NC SENSE4A V EE SENSE4B NC PWRMD1 V EE NC MSD CPD GP0 CND GP1 DPD AUTO DND V DD V CAP1 DD