MAX14721/ High-Accuracy, Adjustable Power Limiter MAX14722/ MAX14723 General Description Benefits and Features The MAX14721MAX14723 adjustable overvoltage, Robust, High-Power Protection Reduces System undervoltage, and overcurrent protection devices guard Downtime systems against overcurrent faults in addition to positive Wide Input Supply Range: +5.5V to +60V overvoltage and reverse-voltage faults. When used with Programmable Input Supply Overvoltage Setting an optional external p-channel MOSFET, the devices also Up to 40V protect downstream circuitry from voltage faults up to Thermal Foldback Current-Limit Protection Negative Input Tolerance to -60V (for -60V External +60V, -60V (for -60V external pFET rating). The devices feature a low, 76m, on-resistance integrated FET. pFET Rating) Low 76m (typ) R During startup, the devices are designed to charge large ON Reverse Current-Blocking Protection with External capacitances on the output in a continuous mode for pFET applications where large reservoir capacitors are used on the inputs to downstream devices. Additionally, the Enables Safer Startup By Preventing Overheating MAX14721MAX14723 feature a dual-stage, current-limit of FETs mode in which the current is continuously limited to 1x, Dual-Stage Current Limiting 1.5x, and 2x the programmed limit, respectively, for a 1.0x Startup Current (MAX14721) short time after startup. This enables faster charging of 1.5x Startup Current (MAX14722) large loads during startup. 2.0x Startup Current (MAX14723) The MAX14721MAX14723 also feature reverse-current Flexible Design Enables Reuse and Less and overtemperature protection. The devices are available Requalification in a 20-pin (5mm x 5mm) TQFN package and operate Adjustable OVLO and UVLO Thresholds over a -40C to 125C temperature range. Programmable Forward Current Limit From 0.2A Applications to 2A with 15% Accuracy Over Full Temperature Industrial Power Systems Range Control and Automation Normal and High-Voltage Enable Inputs Motion System Drives (EN and HVEN) Human Machine Interfaces Protected External pFET Gate Drive High-Power Applications Saves Board Space and Reduces External BOM Count 20-Pin, 5mm x 5mm TQFN Package Ordering Information appears at end of data sheet. Integrated nFET Typical Application Circuit VIN *R1, R2, R3, AND R4 ARE ONLY REQURED FOR ADJUSTABLE UVLO/ C C IN IN C OVLO FUNCTIONALITY. OTHERWISE, TIE THE PIN TO GND TO USE THE GP IN IN IN INTERNAL, PREPROGRAMMED VIN THRESHOLD. R1* OUT UVLO SYSTEM POWER CONTROLLER OUT PROTECTED 220k R2* POWER SYSTEM OUT ADC MAX14721 INPUT MAX14723 V COUT IN R3* OVLO HVEN R4* SETI GND RIPEN ENB HVEN x CLTS2 FLAG FAULT 10k EN EN CLTS1 GND 19-7370 Rev 3 11/17MAX14721/ High-Accuracy, Adjustable Power Limiter MAX14722/ MAX14723 Absolute Maximum Ratings (All voltages referenced to GND.) SETI................................................-0.3V to min(V + 0.3V, 6V) IN IN (Note 1) ..........................................................-0.3V to +60.5V Continuous Power Dissipation (T = +70C) A OUT ..............................................................-0.3V to V + 0.3V TQFN (derate 31.3mW/C above +70C) ..................2500mW IN HVEN (Note 1) .............................................-0.3V to V + 0.3V Operating Temperature Range ......................... -40C to +125C IN GP .....................................max (-0.3V, V - 20V) to V + 0.3V Junction Temperature ......................................................+150C IN IN UVLO, OVLO ...............................-0.3V to min (V + 0.3V, 20V) Storage Temperature Range ............................ -65C to +150C IN FLAG, EN, RIPEN, CLTS1, CLTS2 .........................-0.3V to +6V Lead Temperature (soldering, 10s) .................................+300C Maximum Current into IN (DC) (Note 2) .................................2A Soldering Temperature (reflow) .......................................+260C Note 1: An external pFET or diode is required to achieve negative input protection. Note 2: DC current-limited by R as well as by thermal design. SETI Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information PACKAGE TYPE: 20 TQFN Package Code T2055+3C Outline Number 21-0140 Land Pattern Number 90-0008 THERMAL RESISTANCE, FOUR-LAYER BOARD Junction to Ambient ( ) 32C/W JA Junction to Case ( ) 3C/W JC For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a +, , or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Maxim Integrated 2 www.maximintegrated.com