EVALUATION KIT AVAILABLE MAX14808/MAX14809 Octal Three-Level/Quad Five-Level High-Voltage 2A Digital Pulsers with T/R Switch General Description Benefits and Features The MAX14808/MAX14809 octal three-level/quad five- S Save Space (Optimized for High-Channel-Count level, high-voltage (HV) pulser devices generate high- Systems/Portable Systems) frequency HV bipolar pulses (up to Q105V) from low- High Density voltage control logic inputs for driving piezoelectric 8 Channels (Three-Level Operation) transducers in ultrasound systems. All eight channels 4 Channels (Five-Level Operation) in have embedded overvoltage-protection diodes and an One Package integrated active return-to-zero clamp. Both devices have Integrated Low-Power T/R Switches (MAX14808) embedded independent (floating) power supplies (FPS) DirectDrive Architecture Eliminates External and level shifters that allow signal transmission without High-Voltage Capacitor the need for external HV capacitors. The MAX14808 also No External Floating Power Supply (FPS) features eight integrated transmit/receive (T/R) switches. Required The MAX14809 does not have the T/R switch function. S High Performance (Designed to Enhance Image The devices feature two modes of operation: an octal Quality) three-level pulser mode (with integrated active return- Excellent -43dBc (typ) THD for Second to-zero clamp) or a quad five-level pulser mode. In octal Harmonic at 5MHz three-level pulser mode, each channel is controlled by Sync Function Eliminates Effects of FPGA Jitter two logic inputs (DINN /DINP ) and the active return and Improves Performance in Doppler Mode to zero features half the current driving of the pulser 1A Low Propagation Delay 18ns (typ) (typ). In quad five-level pulser mode, each channel is Strong Active Return to Zero controlled by three logic inputs and the active return to zero has the same current driving of the pulser 2A (typ). S Save Power Low Quiescent Power Dissipation (5.7mW/ The devices can operate both in clocked and transparent mode. In clocked mode, data inputs can be synchronized Channel in Octal Mode) with a clean differential or single-ended clock to reduce Programmable Current Capability phase noise associated with FPGA output signals that are Shutdown Mode and Disable Transmit Mode detrimental for Doppler analysis. In transparent mode, the synchronization feature is disabled and output reflects Applications the data input after a 18ns delay. Both devices feature Ultrasound Medical Imaging adjustable maximum current (0.5A to 2A) to reduce power consumption when full current capability is not required. Industrial Flaw Detection The devices feature integrated grass-clipping diodes Piezoelectric Drivers (with low parasitic capacitance) for receive (Rx) and Test Equipment transmit (Tx) isolations. Both devices feature a damping circuit that can be activated as soon as the transmit burst is over. The damping circuit has a typical on-resistance of 500I. It fully discharges the pulsers output internal node Ordering Information and Functional Diagram appear at end before the grass-clipping diodes. of data sheet. The devices are available in a 68-pin (10mm x 10mm) TQFN package with an exposed pad and are specified over the -40NC to +85NC extended temperature range. DirectDrive is a registered trademark of Maxim Integrated Products, Inc. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14808.related. For pricing, delivery, and ordering information, please contact Maxim Direct 19-6438 Rev 2 1/14 at 1-888-629-4642, or visit Maxims website at www.maximintegrated.com.MAX14808/MAX14809 Octal Three-Level/Quad Five-Level High-Voltage 2A Digital Pulsers with T/R Switch ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) THP Logic Output Voltage Range ........................-0.3V to +5.6V V Logic Supply Voltage Range .......................-0.3V to +5.6V V , V Output Voltage DD GPA GPB V Positive Driver Supply Voltage Range .........-0.3V to +5.6V Range .......max (V - 5.6V), (V + 0.6V) to (V + 0.3V) CC PP EE PP V Negative Driver Supply Voltage Range ........-5.6V to +0.3V V , V Output Voltage EE GNA GNB V , V High Negative Range ......(V - 0.3V) to min (V + 0.6V), (V + 5.6V) NNA NNB NN CC NN Supply Voltage Range .....................................-110V to +0.3V Continuous Power Dissipation (T = +70C) A V , V High Positive TQFN (derate 50mW/NC above +70C) ......................4000mW PPA PPB Supply Voltage Range .....................................-0.3V to +110V Operating Temperature Range .......................... -40C to +85C OUT Output Voltage Range .................................V to V Maximum Junction Temperature .....................................+150C NN PP LVOUT Output Voltage Range Storage Temperature Range ............................ -65C to +150C (100mA Maximum Current)............................-1.2V to +1.2V Lead Temperature (soldering, 10s) ................................+300C DINN , DINP , CC , SYNC, LDO EN ..................-0.3V to +5.6V Soldering Temperature (reflow) ......................................+260C CLK, CLK, MODE Voltage Range .......... -0.3V to (V + 0.3V) CC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (B ) ............20C/W Junction-to-Case Thermal Resistance (B ) ..................0.5C/W JA JC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (V = +3V, V = +5V, V = -5V, V = +100V, V = -100V, V = +100V, V = -100V, 1F bypass capacitor between DD CC EE PPA NNA PPB NNB V and V , 1FF bypass capacitor between V and V , 1F bypass capacitor between V and V , 1F bypass GNA NNA GNB NNB GPA PPA capacitor between V and V , V = 0V, no load, unless otherwise noted. Typical values are at T = +25C.) (Note 2) GPB PPB LDO EN A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES (V , V , V , V , V ) DD CC EE PP NN Logic Supply Voltage V +1.7 +3 +5.25 V DD Positive Drive Supply Voltage V +4.9 +5 +5.1 V CC Negative Drive Supply Voltage V -5.1 -5 -4.9 V EE High-Side Supply Voltage V 0 +105 V PP Low-Side Supply Voltage V -105 0 V NN V - GN External Low-Side LDO Voltage LDO EN = high 5 5.3 5.5 V V NN V - PP External High-Side LDO Voltage LDO EN = high 5 5.3 5.5 V V GP External Floating Power-Supply I LDO EN = high (Note 3) 50 mA VGN Current from V GN External Floating Power-Supply I LDO EN = high (Note 3) 85 mA VGP Current from V GP LOGIC INPUTS/OUTPUTS (DINN , DINP , MODE , SYNC, CC , LDO EN) Low-Level Input Threshold V 0.2 x V V IL DD High-Level Input Threshold V 0.8 x V V IH DD Logic Input Capacitance C 4 pF IN Maxim Integrated 2