EVALUATION KIT AVAILABLE MAX17525 High-Accuracy, Adjustable Power Limiter General Description Benefits and Features The MAX17525 adjustable overvoltage, undervoltage, Robust, High-Power Protection Reduces System and overcurrent protection device guards systems against Downtime Wide Input-Supply Range: +5.5V to +60V overcurrent faults in addition to positive overvoltage and reverse-voltage faults. When used with an optional external Programmable Input-Supply Overvoltage Setting Up To 40V pMOSFET, the device also protects downstream circuitry from voltage faults up to +60V, -60V (for -(60V +V ) -60V Negative Input Tolerance with External OUT pFET (for -(60 + V ) External pFET Rating) external pFET rating). The device features a low, 31m, OUT Low 31m (typ) R on-resistance integrated FET. ON Reverse Current-Blocking Protection with External During startup, the MAX17525 is designed to charge pFET large capacitances on the output in a continuous mode for applications where large reservoir capacitors are used Enables Fast Startup and Brownout Recovery on the inputs to downstream devices. Two additional part Thermal Foldback Current-Limit Protection options that feature a dual-stage, current-limit mode in 1.5x, 2x Startup Current Limit Options which the current is continuously limited to 1.5x and 2x Flexible Design Enables Reuse and Less the programmed limit are available upon request. These Requalification options enable faster charging of large load capacitances Adjustable OVLO and UVLO Thresholds during startup. Programmable Forward Current Limit From 0.6A The MAX17525 also features reverse-current and to 6A with 15% Accuracy Over Full Temperature overtemperature protection. The device is available in a Range 20-pin (5mm x 5mm) TQFN package and operate over Normal and High-Voltage Enable Inputs the -40C to 125C temperature range. (EN and HVEN) Applications Protected External pFET Gate Drive Industrial Power Systems Saves Board Space and Reduces External BOM Control and Automation Count Motion System Drives 20-Pin 5mm x 5mm TQFN Package Human Machine Interfaces Integrated nFET High-Power Applications Ordering Information appears at end of data sheet. Typical Application Circuit VIN *R1, R2, R3, AND R4 ARE ONLY REQURED FOR ADJUSTABLE C IN CIN IC UVLO/OVLO FUNCTIONALITY. OTHERWISE, TIE THE PIN TO GP IN IN IN IN IN GND TO USE THE INTERNAL, VIN R1* OUT PREPROGRAMMED SYSTEM POWER UVLO THRESHOLD. CONTROLLER OUT PROTECTED 220k R2* POWER SYSTEM OUT ADC INPUT MAX17525 V COUT IN R3* OUT OVLO HVEN OUT R4* SETI GND RIPEN ENB HVEN x CLTS2 FLAG FAULT 10k EN EN CLTS1 GND 19-8572 Rev 2 12/17MAX17525 High-Accuracy, Adjustable Power Limiter Absolute Maximum Ratings (All voltages referenced to GND.) SETI...............................................-0.3V to min (V + 0.3V, 6V) IN IN (Note 1) .............................................................-0.3V to +62V Continuous Power Dissipation (T = +70C) A OUT ..............................................................-0.3V to V + 0.3V TQFN (derate 34.5mW/C above +70C) ..................2758mW IN HVEN (Note 1) .............................................-0.3V to V + 0.3V Operating Temperature Range ..........................-40C to +125C IN GP .....................................max (-0.3V, V - 20V) to V + 0.3V Junction Temperature ......................................................+150C IN IN UVLO, OVLO ...............................-0.3V to min (V + 0.3V, 20V) Storage Temperature Range .............................-65C to +150C IN FLAG, EN, RIPEN, CLTS1, CLTS2 .........................-0.3V to +6V Lead Temperature (soldering, 10s) .................................+300C Maximum Current Into IN (DC) (Note 2) ..............................6.9A Soldering Temperature (reflow) .......................................+260C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: An external pFET or diode is required to achieve negative input protection. Note 2: DC current-limited by R , as well as by thermal design. SETI Package Information PACKAGE TYPE: 20 TQFN Package Code T2055+5C Outline Number 21-0140 Land Pattern Number 90-0010 THERMAL RESISTANCE, FOUR-LAYER BOARD Junction to Ambient ( ) 29C/W JA Junction to Case ( ) 2C/W JC For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a +, , or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Maxim Integrated 2 www.maximintegrated.com