EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX17673/MAX17673A Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators General Description Benefits and Features MAX17673/MAX17673A power management integrated Reduces External Components and Total Cost circuits (PMIC) integrate a 60V high voltage (HV), high Synchronous Operation for High Efficiency efficiency synchronous DC-DC buck regulator and two Internal Compensation for a Wide Output Voltage Range 5.5V high efficiency synchronous DC-DC buck regulators. All three regulators offer integrated power MOSFETs. All-Ceramic Capacitors,Compact Layout The HV regulator operates from a 4.5V to 60V input volt- Integrates Three DC-DC Regulators Wide 4.5V to 60V Input Voltage Range for the HV age range and the LV regulators operate from a 2.7V to 5.5V input voltage range. The HV regulator supports load Regulator. 2.7V to 5.5V Input Range for LV Regulators. currents up to 1.5A, and can regulate output voltages from 0.9V to 5.5V. The LV regulators support load currents up to Adjustable 0.9V to 5.5V Output for the HV Regula- tor and 0.75V up to 4.8V Output for LV Regulators 1A, and can regulate output voltages from 0.75V to 4.8V. Delivers up to 1.5A Load Current for the HV Regu- MAX17673/MAX17673A offer independent peak cur- lator and 1A Load Current for LV Regulators rent mode control, hiccup mode overcurrent protection, Adjustable Switching Frequency: 250KHz to ENABLE input and Power OK signal in the three regu- 800KHz for HV Regulator and 1MHz to 4MHz for lators. The switching frequency is adjustable between LV Regulators 1MHz and 4MHz in the LV regulators, and the HV regula- Programmable LV / HV Switching Frequency Ratio tor can be programmed to run at a fractional switching (2, 3, 4, 5, 6, 7, 8) frequency of the LV regulators. The HV regulator offers EN/UVLO for HV buck and EN for LV regulators an adjustable soft-start function, while the LV regulators Reduces Power Dissipation present internally fixed soft-start. Users can choose to 550A in PFM and 10.2mA in PWM Mode operate the devices in either pulse frequency modulation Quiescent Current (PFM) or forced pulse width modulation (PWM) scheme. Peak Efficiency > 92% The MAX17673A offers external clock synchronization. Auxiliary Bootstrap LDO for Improved Efficiency The devices are available in a 28-pin, 5mm x 5mm TQFN PFM Mode for High Light-Load Efficiency package and operates over a -40C to +125C tempera- 7.4A Shutdown Current ture range. Operates Reliably in Adverse Industrial Environments Peak-Current Limit Protection Applications Hiccup Mode Overload Protection Industrial Control Power Supplies Soft-Start Reduces Inrush Current During Startup FPGA/CPLD Power Supplies (Adjustable for HV Regulator) Distributed Supply Regulation Built-In Output-Voltage Monitoring with POKH, POKA, and POKB Base Station Power Supplies Monotonic Startup into Prebiased Load High Voltage Single Board Systems Overtemperature Protection Dynamic Mode Change for On-the-Fly Shift Between PFM and PWM Mode -40C to +125C Operating Temperature Range Ordering Information appears at end of data sheet. Complies with CISPR22(EN55022) Class B Conducted and Radiated Emissions 19-100403 Rev 2 11/19MAX17673/MAX17673A Integrated 4.5V to 60V Synchronous 1.5A HV Buck and Dual 2.7V to 5.5V, 1A Buck Regulators Absolute Maximum Ratings INH to PGND .........................................................-0.3V to +65V SSH, RT, FDIV to GND ............................ -0.3V to (V + 0.3V) CC ENH to GND ..........................................................-0.3V to +65V LXH Total RMS Current ......................................................1.6A BSTH to PGND .....................................................-0.3V to +70V LXA, LXB Total RMS Current .............................................1.1A LXH to PGND .......................................... -0.3V to (V + 0.3V) PGNDA, PGNDB, PGNDH to GND ........................-0.3V to 0.3V INH BSTH to LXH ...........................................................-0.3V to +6V Output Short-Circuit Duration ....................................Continuous BSTH to V .........................................................-0.3V to +65V Continuous Power Dissipation CC INA, INB to PGND ...................................................-0.3V to +6V (Multilayer Board) (T = +70C, derate A ENA, ENB to GND .................................................-0.3V to +6V 34.5mW/C above +70C.) .....................................2758.6mW LXA to PGND .......................................... -0.3V to (V + 0.3V) Operating Temperature Range (Note 1) ........... -40C to +125C INA LXB to PGND .......................................... -0.3V to (V + 0.3V) Storage Temperature Range ............................ -65C to +160C INB EXTVCC, V to GND ............................................-0.3V to +6V Lead Temperature (soldering, 10s) .................................+300C CC FBH, FBA, FBB, POKH, POKA, POKB, MODE/SYNC to GND ..........................................-0.3V to +6V Note 1: Junction temperature greater than +125C degrades operating lifetimes. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information PACKAGE TYPE: 28 TQFN Package Code T2855+6C Outline Number 21-0140 Land Pattern Number 90-0026 THERMAL RESISTANCE, FOUR-LAYER BOARD: Junction to Ambient ( ) +29 C/W JA Junction to Case ( ) +2 C /W JC For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a +, , or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Maxim Integrated 2 www.maximintegrated.com