EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply General Description Features The MAX1932 generates a low-noise, high-voltage out- Unique Architecture Delivers Excellent Accuracy for put to bias avalanche photodiodes (APDs) in optical Improved System Performance receivers. Very low output ripple and noise is achieved 0.5% Accurate Output Low Ripple Output (< 1mV) by a constant-frequency, pulse-width modulated (PWM) boost topology combined with a unique architecture that Protection Features Guarantee Safe Operation maintains regulation with an optional RC or LC post filter Accurate High-Side Current Limit inside its feedback loop. A precision reference and error Avalanche Indicator Flag amplifier maintain 0.5% output voltage accuracy. Output-Voltage Flexibility Facilitates Multiple The MAX1932 protects expensive APDs against adverse Applications and Design Approaches operating conditions while providing optimal bias. 4.5V to 90V Output Traditional boost converters measure switch current for Set Output Voltage via 8-Bit SPI-Compatible protection, whereas the MAX1932 integrates accurate Internal DAC, External DAC, or External Resistors high-side current limiting to protect APDs under ava- Small Circuit Footprint Reduces Equipment Size lanche conditions. A current-limit flag allows easy calibra- 12-Pin, 4mm x 4mm Thin QFN Package tion of the APD operating point by indicating the precise Circuit Height < 2mm point of avalanche breakdown. The MAX1932 control Commonly Available 2.7V to 5.5V Input Voltage scheme prevents output overshoot and undershoot to Range provide safe APD operation without data loss. The output voltage can be accurately set with either exter- nal resistors, an internal 8-bit DAC, an external DAC, or other voltage source. Output span and offset are inde- Ordering Information pendently settable with external resistors. This optimizes the utilization of DAC resolution for applications that may PART TEMP RANGE PIN-PACKAGE require limited output voltage range, such as 4.5V to 15V, MAX1932ETC -40C to +85C 12 Thin QFN 4.5V to 45V, 20V to 60V, or 40V to 90V. Applications Optical Receivers and Modules Typical Application Circuit Fiber Optic Network Equipment Telecom Equipment Laser Range Finders INPUT 2.7V TO 5.5V PIN Diode Bias Supply VIN Pin Configuration APD BIAS OUTPUT MAX1932 4.5V TO 90V COMP GATE 12 11 10 SCLK 1 9 GND CS CS+ DAC INPUTS SCLK DIN 2 8 COMP MAX1932 CS- DIN CL 3 7 FB AVALANCHE CL INDICATOR 4 5 6 FLAG FB GND DACOUT 19-2555 Rev 3 10/19 CS CS+ CS- VIN DACOUT GATEMAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply Absolute Maximum Ratings VIN to GND .............................................................-0.3V to +6V Operating Temperature Range ........................... -40C to +85C DIN, SCLK, CS, FB to GND ....................................-0.3V to +6V Junction Temperature ......................................................+150C COMP, DACOUT, GATE, CL to GND ..........-0.3V to (V +0.3V) Storage Temperature Range ............................ -65C to +150C IN CS+, CS- to GND ................................................-0.3V to +110V Lead Temperature (soldering 10s) ..................................+300C Continuous Power Dissipation (T = +70C) A 12-Pin Thin QFN (derate 16.9mW/C above +70C) ....1349mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (V = 3.3V, CS = SCLK = D = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, T = 0C to +85C, unless otherwise noted.) IN IN A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL Input Supply Range V 2.7 5.5 V IN V Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V IN Operating Supply Current I 0.5 1 mA IN V Shutdown Supply Current I 00 hex loaded to DAC 25 65 A IN SHDN Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 1 2.0 M Current-Limit Threshold 1.80 2.00 2.20 V for CS+/CS- Common-Mode Rejection CS+ = 3V to 100V 0.005 %/V of Current Threshold Gate-Driver Resistance Gate high or low, I = 50mA 5 10 GATE Input Bias Current -25 +25 nA T = +25C 1.24375 1.2500 1.25625 A FB Voltage V V FB T = 0C to +85C 1.24250 1.2500 1.25750 A FB Voltage Temperature TCV 0.0007 %/C FB Coefficient FB to COMP Transconductance COMP = 1.5V 50 110 200 S COMP Pulldown Resistance DAC code = 00 hex 100 in Shutdown DACOUT to FB Voltage Difference DAC code = FF hex -3 +3 mV DACOUT Differential Nonlinearity DAC Code = 01 to FF hex, -1 +1 LSB (Note 1) DAC guaranteed monotonic DACOUT Voltage Temperature TCV 0.0007 %/C DACOUT Coefficient DAC code = 0F to FF hex, source or sink DACOUT Load Regulation -1 +1 mV 50A Switching Frequency f 250 300 340 kHz OSC GATE Maximum On-Time t 3 s ON Maxim Integrated 2 www.maximintegrated.com