19-6333 Rev 0 5/12 MAX31855PMB1 Peripheral Module General Description Features The MAX31855PMB1 peripheral module provides the S Converts Output of a K-Type Thermocouple necessary hardware to interface the MAX31855 cold- Directly to a Signed 14-Bit Digital Word junction compensated thermocouple-to-digital converter S Cold-Junction Compensation to any system that utilizes PmodK-compatible expansion S 14-Bit, 0.25NC Resolution ports. The IC performs cold-junction compensation and S Detects Thermocouple Shorts to GND or VCC digitizes the signal from a thermocouple. Versions of the IC are available that operate with a K-, J-, N-, T-, R-, or S Detects Open Thermocouple E-type thermocouple. This module is set up to operate S 6-Pin Pmod-Compatible Connector (SPI) with a K-type thermocouple. The data is output in a signed S Example Software Written in C for Portability 14-bit, SPI-compatible, read-only format. This converter resolves temperatures to 0.25NC, allows readings as high S RoHS Compliant as +1800NC and as low as -270NC, and exhibits thermo- S Proven PCB Layout couple accuracy of Q2NC for temperatures ranging from S Fully Assembled and Tested -200NC to +700NC for K-type thermocouples. For full range accuracies, other thermocouple types, and Ordering Information appears at end of data sheet. detailed information regarding operation of the IC, refer to the MAX31855 IC data sheet. Note: K-type thermocouple is not included with Maxim Peripheral Module collections. MAX31855PMB1 Photo Pmod is a trademark of Digilent Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.MAX31855PMB1 Peripheral Module Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY DESCRIPTION Not installed, ceramic capacitors K-type thermocouple socket C1, C4 0 J2 1 (0805) Omega PCC-SMP-K-5-ROHS 470I ferrite beads (0603) 0.1FF Q10%, 16V X7R ceramic L1, L2 2 Murata BLM18PG471SN1D C2 1 capacitor (0603) Murata GRM188R71C104KA01D R1, R2, R3 3 150I Q5% resistors (0603) 0.01FF Q10%, 16V X7R ceramic Thermocouple to digital IC C3 1 capacitor (0603) U1 1 (8 SO) Murata GRM188R71C103KA01D Maxim MAX31855KASA+ 1 K-type thermocouple, mini plug* TVS diode (3 SOT3) D1 1 ON Semi NUP2105TL1G 1 PCB: EPCB31855PM1 J1 1 6-pin right-angle male header *Thermocouple not included with Maxim peripheral module collections. Component Suppliers SUPPLIER PHONE WEBSITE Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com Omega Engineering 888-826-6342 www.omega.com ON Semiconductor 602-244-6600 www.onsemi.com Note: Indicate that you are using the MAX31855PMB1 when contacting these component suppliers. Table 1. Connector J1 (SPI Communication) Detailed Description PIN SIGNAL DESCRIPTION SPI Interface Chip enable. Must be asserted low to The MAX31855PMB1 peripheral module can plug directly 1 SS enable the SPI interface. into a Pmod-compatible port (configured for SPI) through 2 N.C. Not connected connector J1. For information on the SPI protocol, refer to 3 MISO Serial-data output the MAX31855 IC data sheet. 4 SCK Serial-clock input Connector J1 provides connection of the module to 5 GND Ground the Pmod host. The pin functions and pin assignments adhere to the Pmod standard recommended by Digilent. 6 VCC Power supply See Table 1. The software project (for the SDK) contains several Software and FPGA Code source files intended to accelerate customer evalu- Example software and drivers are available that execute ation and design. These include a base application directly without modification on several FPGA develop- (maximModules.c) that demonstrates module function- ment boards that support an integrated or synthesized ality and uses an API interface (maximDeviceSpecific microprocessor. These boards include the Digilent Nexys Utilities.c) to set and access Maxim device functions 3, Avnet LX9, and Avnet ZEDBoard, although other plat- within a specific module. forms can be added over time. Maxim provides complete The source code is written in standard ANSI C format, and Xilinx ISE projects containing HDL, Platform Studio, and all API documentation including theory/operation, register SDK projects. In addition, a synthesized bitstream, ready description, and function prototypes are documented in for FPGA download, is provided for the demonstration the API interface file (maximDeviceSpecificUtilities.h & .c). application. The complete software kit is available for download at www.maxim-ic.com. Quick start instructions are also available as a separate document. Maxim Integrated Products 2