MAX5823/MAX5824/ Ultra-Small, Octal Channel, 8-/10-/12-Bit MAX5825 Buffered Output DACs with Internal 2 Reference and I C Interface General Description Benefits and Features The MAX5823/MAX5824/MAX5825 8-channel, low-power, Eight High-Accuracy DAC Channels 12-Bit Accuracy Without Adjustment 8-/10-/12-bit, voltage-output digital-to-analog converters (DACs) include output buffers and an internal 3ppm/C 1 LSB INL Buffered Voltage Output Guaranteed Monotonic Over All Operating reference that is selectable to be 2.048V, 2.500V, or Conditions 4.096V. The MAX5823/MAX5824/MAX5825 accept a Independent Mode Settings for Each DAC wide supply voltage range of 2.7V to 5.5V with extremely low power (6mW) consumption to accommodate most Three Precision Selectable Internal References low-voltage applications. A precision external reference 2.048V, 2.500V, or 4.096V input allows rail-to-rail operation and presents a 100k Internal Output Buffer (typ) load to an external reference. Rail-to-Rail Operation with External Reference 2 The MAX5823/MAX5824/MAX5825 have an I C- 4.5s Settling Time compatible, 2-wire interface that operates at clock rates Outputs Directly Drive 2k Loads up to 400kHz. The DAC output is buffered and has a low Small 6.5mm x 4.4mm 20-Pin TSSOP or Ultra-Small supply current of less than 250A per channel and a low 2.5mm x 2.3mm 20-Bump WLP Package offset error of 0.5mV (typ). On power-up, the MAX5823/ Wide 2.7V to 5.5V Supply Range MAX5824/MAX5825 reset the DAC outputs to zero or Separate 1.8V to 5.5V V Power-Supply Input mid-scale based on the status of M/Z logic input, providing DDIO flexibility for a variety of control applications. The internal 2 Fast 400kHz I C-Compatible, 2-Wire Serial Interface reference is initially powered down to allow use of an Pin-Selectable Power-On-Reset to Zero-Scale or external reference. The MAX5823/MAX5824/MAX5825 Midscale DAC Output allow simultaneous output updates using software LOAD LDAC and CLR For Asynchronous DAC Control commands or the hardware load DAC logic input (LDAC). Three Software-Selectable Power-Down Output The MAX5823/MAX5824/MAX5825 feature a watchdog Impedances function which can be enabled to monitor the I/O interface 1k, 100k, or High Impedance for activity and integrity. A clear logic input (CLR) allows the contents of the CODE and the DAC registers to be cleared asynchronously and Functional Diagram simultaneously sets the DAC outputs to the programmable default value. The MAX5823/MAX5824/MAX5825 are available in a 20-pin TSSOP and an ultra-small, 20-bump VDDIO VDD REF WLP package and are specified over the -40C to +125C MAX5823 MAX5824 INTERNAL REFERENCE/ temperature range. EXTERNAL BUFFER MAX5825 SCL SDA 1 OF 8 DAC CHANNELS Applications ADDR0 CODE DAC 8-/10-/12-BIT 2 I C SERIAL REGISTER LATCH DAC Programmable Voltage and Current Sources ADDR1 INTERFACE OUT0 BUFFER OUT1 CLR Gain and Offset Adjustment OUT2 LDAC (GATE/ OUT3 CLEAR/ CLEAR/ CODE RESET LOAD OUT4 Automatic Tuning and Optical Control RESET) 100kI 1kI OUT5 IRQ WATCHDOG TIMER OUT6 DAC CONTROL LOGIC POWER-DOWN Power Amplifier Control and Biasing OUT7 M/Z Process Control and Servo Loops POR Portable Instrumentation GND Ordering Information appears at end of data sheet. 19-6185 Rev 3 8/19MAX5823/MAX5824/ Ultra-Small, Octal Channel, 8-/10-/12-Bit MAX5825 Buffered Output DACs with Internal 2 Reference and I C Interface Absolute Maximum Ratings V V to GND ................................................-0.3V to +6V Maximum Continuous Current into Any Pin ....................Q50mA DD, DDIO Operating Temperature .................................... -40NC to +125NC OUT , REF to GND....0.3V to the lower of (V + 0.3V) and +6V DD SCL, SDA, IRQ, M/Z, LDAC, CLR to GND .............-0.3V to +6V Storage Temperature ....................................... -65NC to +150NC Lead Temperature (TSSOP only)(soldering, 10s) ...........+300NC ADDR to GND ............................................-0.3V to the lower of Soldering Temperature (reflow) .................................... +260NC (V + 0.3V) and +6V DDIO Continuous Power Dissipation (T = +70NC) A TSSOP (derate at 13.6mW/NC above 70NC) ..............1084mW WLP (derate at 21.3mW/NC above 70NC) ..................1700mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1 TSSOP WLP Junction-to-Ambient Thermal Resistance ( ) ......73.8NC/W Junction-to-Ambient Thermal Resistance ( ) JA JA Junction-to-Case Thermal Resistance ( ) ..............20NC/W (Note 2) ...................................................................47NC/W JC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Note 2: Visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of WLP pack- aging. Electrical Characteristics (V = 2.7V to 5.5V, V = 1.8V to 5.5V, V = 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted.) DD DDIO GND L L A (Note 3) CONDITIONS MIN TYP MAX UNITS PARAMETER SYMBOL DC PERFORMANCE (Note 4) MAX5823 8 Resolution and Monotonicity N MAX5824 10 Bits MAX5825 12 MAX5823 -0.25 Q0.05 +0.25 Integral Nonlinearity (Note 5) INL MAX5824 -0.5 Q0.2 +0.5 LSB MAX5825 -1 Q0.5 +1 MAX5823 -0.25 Q0.05 +0.25 Differential Nonlinearity (Note 5) DNL MAX5824 -0.5 Q0.1 +0.5 LSB MAX5825 -1 Q0.2 +1 Offset Error (Note 6) OE -5 Q0.5 +5 mV Offset Error Drift Q10 FV/NC Gain Error (Note 6) GE -1.0 Q0.1 +1.0 %FS ppm of Gain Temperature Coefficient With respect to V Q3.0 REF FS/NC Zero-Scale Error 0 +10 mV Full-Scale Error With respect to V -0.5 +0.5 %FS REF Maxim Integrated 2 www.maximintegrated.com