MAX5858A DA9/PD 19-2999 Rev 0 10/03 Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL General Description Features The MAX5858A dual, 10-bit, 300Msps digital-to-analog 10-Bit Resolution, Dual DAC converter (DAC) provides superior dynamic performance 300Msps Update Rate in wideband communication systems. The MAX5858A Integrated 4x/2x/1x Interpolating Filters integrates two 10-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock Internal PLL Multiplier multiplier, and a 1.24V reference. The MAX5858A sup- 2.7V to 3.3V Single Supply ports single-ended and differential modes of operation. Full Output Swing and Dynamic Performance at The MAX5858A dynamic performance is maintained over 2.7V Supply the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of Superior Dynamic Performance -1.0V to +1.25V. 73dBc SFDR at f = 20MHz OUT UMTS ACLR = 63dB at f = 30.7MHz OUT The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Programmable Channel Gain Matching Interpolating filters minimize the design complexity of Integrated 1.24V Low-Noise Bandgap Reference analog reconstruction filters while lowering the data bus Single-Resistor Gain Control and the clock speeds of the digital interface. The PLL multiplier generates all internal, synchronized high- Interleave Data Mode speed clock signals for interpolating filter operation and Differential Clock Input Modes DAC core conversion. The internal PLL helps minimize EV Kit AvailableMAX5858AEVKit system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data Ordering Information mode. This allows the MAX5858A to be updated on a single 10-bit bus. PART TEMP RANGE PIN-PACKAGE The MAX5858A features digital control of channel gain MAX5858AECM -40C to +85C 48 TQFP-EP* matching to within 0.4dB in sixteen 0.05dB steps. *EP = Exposed paddle. Channel matching improves sideband suppression in analog quadrature modulation applications. The on- chip 1.24V bandgap reference includes a control Pin Configuration amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal ref- erence can be disabled and an external reference can be applied for high-accuracy applications. 48 47 46 45 44 43 42 41 40 39 38 37 The MAX5858A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single 1 36 REFO EP supply. The DAC supports three modes of power-con- 2 35 DA8/DACEN REN trol operation: normal, low-power standby, and com- DA7/F2EN 3 34 PLLF plete power-down. In power-down mode, the operating DA6/F1EN 4 33 PGND current is reduced to 1A. DA5/G3 5 32 PV DD DGND 6 31 CLKXN The MAX5858A is packaged in a 48-pin TQFP with MAX5858A DV 7 30 CLKXP DD exposed paddle (EP) for enhanced thermal dissipation DA4/G2 8 29 PLLEN and is specified for the extended (-40C to +85C) opera- DA3/G1 9 28 LOCK ting temperature range. DA2/G0 10 27 CW DA1 11 26 DB0 Applications DA0 12 25 DB1 Communications SatCom, LMDS, MMDS, HFC, DSL, WLAN, 13 14 15 16 17 18 19 20 21 22 23 24 Point-to-Point Microwave Links Wireless Base Stations TQFP-EP Direct Digital Synthesis NOTE: EXPOSED PADDLE CONNECTED TO GND. Instrumentation/ATE Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLE DB9 DV DD DB8 DGND DB7 AV DD DB6 OUTPA DB5 OUTNA DV AGND DD DGND OUTPB CLK OUTNB IDE AV DD REFR DB4 DB3 N.C. DB2 N.C.Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ABSOLUTE MAXIMUM RATINGS AV , DV , PV to AGND, DGND, PGND ..........-0.3V to +4V AGND to DGND, DGND to PGND, DD DD DD DA9DA0, DB9DB0, CW, REN, PLLF, PLLEN to AGND, AGND to PGND..................................................-0.3V to +0.3V DGND, PGND........................................................-0.3V to +4V Maximum Current into Any Pin IDE to AGND, DGND, PGND...................-0.3V to (DV + 0.3V) (excluding power supplies) ............................................50mA DD CLKXN, CLKXP to PGND .........................................-0.3V to +4V Continuous Power Dissipation (T = +70C) A OUTP , OUTN to AGND.......................-1.25V to (AV + 0.3V) 48-Pin TQFP-EP (derate 36.2mW/C above +70C) ....2.899W DD CLK, LOCK to DGND...............................-0.3V to (DV + 0.3V) Operating Temperature Range ...........................-40C to +85C DD REFR, REFO to AGND .............................-0.3V to (AV + 0.3V) Storage Temperature Range .............................-65C to +150C DD Junction Temperature......................................................+150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AV = DV = PV = 3V, AGND = DGND = PGND = 0, f = 165Msps, no interpolation, PLL disabled, external reference, DD DD DD DAC V = 1.2V, I = 20mA, output amplitude = 0dB FS, differential output, T = T to T , unless otherwise noted. T > +25C REFO FS A MIN MAX A guaranteed by production test. T < +25C guaranteed by design and characterization. Typical values are at T = +25C.) A A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 10 Bits Integral Nonlinearity INL R = 0 -1.25 0.5 +1.25 LSB L Differential Nonlinearity DNL Guaranteed monotonic, R = 0 -0.75 0.25 +0.75 LSB L Offset Error V -0.5 0.1 +0.5 LSB OS Internal reference (Note 1) -10 1.6 +11 Gain Error (See Gain Error GE % Parameter Definitions Section) External reference -8 1.2 +8 DYNAMIC PERFORMANCE Maximum DAC Update Rate f 4x/2x interpolation modes 300 Msps DAC Glitch Impulse 5 pV-s f = 5MHz, OUT 68 76 T +25C A f = 165Msps f = 20MHz 73 DAC OUT f = 50MHz 66 Spurious-Free Dynamic Range to OUT SFDR dBc Input Update Rate Nyquist f = 70MHz 65 OUT f = 5MHz 76 OUT f = 300Msps, DAC f = 40MHz 73 OUT 2x interpolation f = 60MHz 72 OUT f = 200Msps, 2x interpolation, DAC 85 f = 40MHz, span = 20MHz OUT Spurious-Free Dynamic Range SFDR dBc Within a Window f = 165Msps, f = 5MHz, DAC OUT 76.5 85 span = 4MHz Multitone Power Ratio, 8 Tones, MTPR f = 165Msps, f = 20MHz 76 dBc DAC OUT ~300kHz Spacing Adjacent Channel Leakage Ratio ACLR f =122.88Msps, f = 30.72MHz 63 dB DAC OUT with UMTS 2 MAX5858A