EVALUATION KIT AVAILABLE MAX5860 Scalable High-Density Downstream Cable QAM Modulator General Description Benefits and Features The MAX5860 is an integrated, high-density, downstream Integrated Downstream Cable QAM Modulator High-Density: Scalable Up to 128 QAM Channels cable QAM modulator, digital upconverter (DUC) and Factory Preset for 32, 48, 64, 96, or 128 QAM RF digital-to-analog converter (RF-DAC). The device Channels performs QAM mapping, pulse shaping and digital RF Soft-Key Field-Upgradeable in Steps of 8 QAMs* upconversion of forward-error-correction (FEC) encoded 14-Bit 4.6Gsps RF-DAC data with full agility and drives a single RF-port using a DOCSIS 3.0 DRFI Compliant 14-bit 4.6Gsps DAC. The device digitally synthesizes RF High ly Flexible and Configu rable signals with up to 128 DOCSIS-compliant 6MHz QAM RRC Filters Support ITU-T J.83 Annex A, B, and C channels (or up to 96 8MHz QAM channels). The device 1MHz to 8MHz Channel Bandwidth has scalable QAM capacity and provides high-density Full Carrier Agility within Each of Four 192MHz Blocks QAM modulation with very low power dissipation (45mW/ Block Agility within 950MHz Output Bandwidth QAM typical) in a compact 12mm x 17mm footprint. Reconfigurable Without Service Interruption The device accepts FEC-encoded CMOS data (symbols) Input Symbol Rate: 1Msym/s to 7.14Msym/s on up to four 10-bit input ports that accept up to 32 time- Independently Set for Each Channel interleaved digital data streams each. Each channel fea- Integrated QAM Mapper (16/32/64/128/256-QAM) tures an individually configurable QAM mapper, RRC filter, Supports All ITU-T J.83-Defined Constellations and arbitrary rate resampler (ARR). The device performs Four CMOS Input Ports Support Up to 1024-QAM pulse shaping, resampling, interpolation and quadrature Additional Features Ease RF Design modulation of input data, supporting all data rates defined in Programmable Digital Predistortion DOCSIS 3.0 and DVB-C. A cascade of interpolation filters, High DAC Output Power 9dBm (CW) Eliminates Pre-amp complex modulators, and channel combiners allow modula- Low Power, Compact Solution tion of the signal to any frequency from 47MHz to 1006MHz. 5.7W at 128 (6MHz) QAMs, f = 4.6Gsps S Integrated direct digital frequency synthesizers allow posi- 12mm x 17mm, 280-Ball FCBGA tioning of the QAM channels with a resolution of 125Hz. The interpolation filters and resamplers provide linear phase and Applications excellent gain flatness. Output data from the last modulator Edge QAM, CMTS, CCAP, IP-QAM is fed to a digital-predistortion (DPD) block that can be used Remote PHY, Coax Media Converters to correct distortion in the devices integrated RF-DAC and Multi-Dweller Unit Mini-Headends output amplifiers external to the device. Ordering Information appears at end of data sheet. Simplified Block Diagram INPUT TIMING ONE PER BLOCK (MAX 32 CHANNELS) ONE PER SUB-BLOCK (MAX 8 CHANNELS) MAX5860 ONE PER CHANNEL INPUT RRC INPUT 4 ARR + 4 + 8 + 2 DATA DATA 2 INTERFACE 14-BIT QAM COMPLEX COMPLEX COMPLEX 4.6Gsps + DPD MAPPER MODULATOR MODULATOR MODULATOR DAC RRC - 4 ARR + 4 + 8 + 2 2 NCO NCO NCO NCO SPI PORT JTAG For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX5860.related. *Contact Maxim to discuss field scalability options from factory reset configurations as low as 8 QAM channels. 19-6546 Rev 0 6/13MAX5860 Scalable High-Density Downstream Cable QAM Modulator TABLE OF CONTENTS General Description ............................................................................ 1 Benefits and Features .......................................................................... 1 Applications .................................................................................. 1 Simplified Block Diagram........................................................................ 1 Absolute Maximum Ratings ...................................................................... 9 Package Thermal Characteristics ................................................................. 9 DC Electrical Characteristics ..................................................................... 9 AC Electrical Characteristics 12 Typical Operating Characteristics ................................................................ 17 Ball Configuration............................................................................. 28 Ball Description .............................................................................. 28 Signal Description ............................................................................ 32 Detailed Description........................................................................... 34 Operational Overview 34 Reference System . 36 Analog Output 36 Clock Inputs . 37 Clock Duty Cycle 37 Input Symbol Interface . 38 Symbol Interface Description 38 Port Input Timing . 38 Handshaking 40 Port Clock 40 Single Data Rate (SDR) 40 Double Data Rate (DDR) . 41 Channel FIFO Operation 42 Modulator and Upconverter Core . 43 DSP Path Block Diagram . 43 Octal Channel Combiner (48MHz Block) . 43 Block Combiners and Digital Upconversion . 44 QAM Mapper . 45 RRC Filter . 45 Arbitrary Rate Resampler . 47 Modulators . 47 Power Adjustment and Power Probes . 47 DPD Function 48 DPDCFG Register Bit Explanation (Address 0x081) 50 Synthesizable Bandwidth vs. Clock Rate . 50 Maxim Integrated 2 www.maximintegrated.com