EVALUATION KIT AVAILABLE MAX5862 High-Density Downstream Cable QAM Modulator General Description Benefits and Features The MAX5862 is an integrated, high-density, downstream Integrated Downstream Cable QAM Modulator High-Density: 8, 16, 24, or 32 QAM Channels cable QAM modulator, digital upconverter (DUC) and 14-Bit 4.6Gsps RF-DAC RF digital-to-analog converter (RF-DAC). The device DOCSIS 3.0 DRFI Compliant performs QAM mapping, pulse shaping and digital RF upconversion of forward-error-correction (FEC) encoded High ly Flexible and Configu rable data with full agility and drives a single RF-port using a RRC Filters Support ITU-T J.83 Annex A, B, and C 14-bit 4.6Gsps DAC. The device digitally synthesizes RF 1MHz to 8MHz Channel Bandwidth Full Carrier Agility within Each of Four 192MHz Blocks signals with up to 32 DOCSIS-compliant 6MHz QAM or Block Agility within 950MHz Output Bandwidth 8MHz QAM channels. The device has fixed QAM capacity Reconfigurable Without Service Interruption and provides high-density QAM modulation with very low Input Symbol Rate: 1Msym/s to 7.14Msym/s power dissipation (4.2W at 32 QAMs) in a compact 12mm Independently Set for Each Channel x 17mm footprint. Integrated QAM Mapper (16/32/64/128/256-QAM) The device accepts FEC-encoded CMOS data (symbols) Supports All ITU-T J.83-Defined Constellations on a single 10-bit input port that accepts up to 32 time-inter- CMOS Input Port Supports Up to 1024-QAM leaved digital data streams. Each channel features an indi- Additional Features Ease RF Design vidually configurable QAM mapper, RRC filter, and arbitrary Programmable Digital Predistortion rate resampler (ARR). The device performs pulse shaping, High DAC Output Power 9dBm (CW) Eliminates Pre-amp resampling, interpolation and quadrature modulation of input Low Power, Compact Solution data, supporting all data rates defined in DOCSIS 3.0 and 4.2W at 32 (6MHz) QAMs, f = 4.6Gsps DVB-C. A cascade of interpolation filters, complex modula- S 12mm x 17mm, 280-Ball FCBGA tors, and channel combiners allow modulation of the signal to any frequency from 47MHz to 1006MHz. Integrated direct Applications digital frequency synthesizers allow positioning of the QAM Edge QAM, CMTS, CCAP, IP-QAM channels with a resolution of 125Hz. The interpolation filters Remote PHY, Coax Media Converters and resamplers provide linear phase and excellent gain flat- Multi-Dweller Unit Mini-Headends ness. Output data from the last modulator is fed to a digital- predistortion (DPD) block that can be used to correct distor- tion in the devices integrated RF-DAC and output amplifiers external to the device. Ordering Information appears at end of data sheet. Simplified Block Diagram INPUT TIMING ONE PER BLOCK (MAX 32 CHANNELS) ONE PER SUB-BLOCK (MAX 8 CHANNELS) MAX5862 ONE PER CHANNEL INPUT RRC INPUT 4 ARR 4 + 8 + 2 DATA + DATA 2 INTERFACE 14-BIT QAM COMPLEX COMPLEX COMPLEX DPD 4.6Gsps + MAPPER MODULATOR MODULATOR MODULATOR DAC RRC - 4 ARR 4 + 8 + 2 + 2 NCO NCO NCO NCO SPI PORT JTAG For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX5862.related. 19-6648 Rev 0 7/13MAX5862 High-Density Downstream Cable QAM Modulator TABLE OF CONTENTS General Description ............................................................................ 1 Benefits and Features .......................................................................... 1 Applications .................................................................................. 1 Simplified Block Diagram........................................................................ 1 Absolute Maximum Ratings ...................................................................... 9 Package Thermal Characteristics ................................................................. 9 DC Electrical Characteristics ..................................................................... 9 AC Electrical Characteristics 12 Typical Operating Characteristics ................................................................ 17 Ball Configuration............................................................................. 25 Ball Description .............................................................................. 25 Signal Description ............................................................................ 28 Detailed Description........................................................................... 30 Operational Overview 30 Reference System . 32 Analog Output 32 Clock Inputs . 33 Clock Duty Cycle 33 Input Symbol Interface . 34 Symbol Interface Description 34 Port Input Timing . 34 Handshaking 36 Port Clock 36 Single Data Rate (SDR) 36 Double Data Rate (DDR) . 38 Channel FIFO Operation 39 Modulator and Upconverter Core . 39 DSP Path Block Diagram . 39 Octal Channel Combiner (48MHz Block) . 40 Block Combiners and Digital Upconversion . 41 QAM Mapper . 41 RRC Filter . 41 Rate Resampler 43 Modulators . 43 Power Adjustment and Power Probes . 43 DPD Function 44 DPDCFG Register Bit Explanation (Address 0x081) 46 Synthesizable Bandwidth vs. Clock Rate . 46 Maxim Integrated 2 www.maximintegrated.com