MAX5865 19-2916 Rev 1 10/03 Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End General Description Features The MAX5865 ultra-low-power, highly integrated analog Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs front end is ideal for portable communication equipment Ultra-Low Power such as handsets, PDAs, WLAN, and 3G wireless termi- 75.6mW at f = 40MHz (Transceiver Mode) nals. The MAX5865 integrates dual 8-bit receive ADCs CLK and dual 10-bit transmit DACs while providing the high- 64mW at f = 22MHz (Transceiver Mode) CLK est dynamic performance at ultra-low power. The ADCs Low-Current Idle and Shutdown Modes analog I-Q input amplifiers are fully differential and Excellent Dynamic Performance accept 1V full-scale signals. Typical I-Q channel P-P 48.4dB SINAD at f = 5.5MHz (ADC) IN phase matching is 0.2 and amplitude matching is 70dB SFDR at f = 2.2MHz (DAC) OUT 0.05dB. The ADCs feature 48.4dB SINAD and 70dBc spurious-free dynamic range (SFDR) at f = 5.5MHz and IN Excellent Gain/Phase Match f = 40MHz. The DACs analog I-Q outputs are fully CLK 0.2 Phase, 0.05dB Gain at f = 5.5MHz (ADC) IN differential with 400mV full-scale output, and 1.4V com- Internal/External Reference Option mon-mode level. Typical I-Q channel phase matching is 0.15 and gain matching is 0.05dB. The DACs also +1.8V to +3.3V Digital Output Level (TTL/CMOS feature dual 10-bit resolution with 72dBc SFDR, and Compatible) 57dB SNR at f = 2.2MHz and f = 40MHz. OUT CLK Multiplexed Parallel Digital Input/Output for The ADCs and DACs operate simultaneously or indepen- ADCs/DACs dently for frequency-division duplex (FDD) and time-divi- sion duplex (TDD) modes. A 3-wire serial interface Miniature 48-Pin Thin QFN Package (7mm 7mm) controls power-down and transceiver modes of opera- Evaluation Kit Available (Order MAX5865EVKIT) tion. The typical operating power is 75.6mW at f = CLK 40Msps with the ADCs and DACs operating simultane- ously in transceiver mode. The MAX5865 features an Functional Diagram internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5865 operates on a +2.7V to +3.3V ana- log power supply and a +1.8V to +3.3V digital I/O power IA+ ADC supply for logic compatibility. The quiescent current is IA- ADC 8.5mA in idle mode and 1A in shutdown mode. The OUTPUT DA0DA7 MAX5865 is specified for the extended (-40C to +85C) MUX QA+ temperature range and is available in a 48-pin thin QFN ADC QA- package. CLK Applications ID+ DAC Narrowband/Wideband CDMA Handsets ID- DAC and PDAs INPUT DD0DD9 MUX QD+ Fixed/Mobile Broadband Wireless Modems DAC QD- 3G Wireless Terminals REFP Ordering Information COM REFN SERIAL PART TEMP RANGE PIN-PACKAGE DIN INTERFACE SCLK REF AND AND SYSTEM 48 Thin QFN-EP* REFIN CS MAX5865ETM -40C to +85C BIAS CONTROL (7mm x 7mm) MAX5865E/D -40C to +85C Dice** *EP = Exposed paddle. MAX5865 **Contact factory for dice specifications. Pin Configuration appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLEUltra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND, OV to OGND................................-0.3V to +3.3V Continuous Power Dissipation (T = +70C) DD DD A GND to OGND.......................................................-0.3V to +0.3V 48-Pin Thin QFN (derate 26.3mW/C above IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, +70C)..............................................................................2.1W REFIN, COM to GND..............................-0.3V to (V + 0.3V) Thermal Resistance .................................................+38C/W DD JA DD0DD9, SCLK, DIN, CS, CLK, Operating Temperature Range ...........................-40C to +85C DA0DA7 to OGND .............................-0.3V to (OV + 0.3V) Junction Temperature......................................................+150C DD Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = 3V, OV = 1.8V, internal reference (1.024V), C 10pF on all digital outputs, f = 40MHz, ADC input amplitude = -0.5dBFS, DD DD L CLK DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C = C = C = 0.33F, Xcvr mode, unless REFP REFN COM otherwise noted. Typical values are at T = +25C, unless otherwise noted.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage V 2.7 3.0 3.3 V DD Output Supply Voltage OV 1.8 V V DD DD ADC oper at ing m ode, f = 5.5MH z, f = IN C LK 25.2 32 40M H z, DAC op er ating m ode, f = 2.2MH z OUT ADC operating mode (Rx), f = 5.5MHz, IN f = 40MH z, DAC digital inputs at zero or 21 CLK OV D D mA DAC operating mode (Tx), f = 2.2MHz, OUT 12.8 f = 40MH z, ADC off V Supply Current CLK DD Standby mode, DAC digital inputs and CLK 2.0 at zero or OV DD Idle mode, DAC digital inputs at zero or 11 OV , f = 40M H z DD CLK Shutdown mode, digital inputs and CLK at 1A zero or OV , CS = OV DD DD ADC operating mode, f = 5.5MHz, f = IN CLK 40Msps, DAC operating mode, f = 3.8 mA OUT 2.2MHz OV Supply Current DD Idle mode, DAC digital inputs at zero or 37.4 OV f = 40M H z DD, CLK A Shutdown mode, DAC digital inputs and 1 CLK at zero or OV , CS = OV DD DD 2 MAX5865