2x INTERPOLATING FILTERS MODULATOR 1x/2x/4x INTERPOLATING FILTERS DATA SYNCH AND DEMUX MAX5898 19-3756 Rev 2 8/10 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs General Description Features 71dB ACLR at f = 61.44MHz (Four-Carrier The MAX5898 programmable interpolating, modulating, OUT WCDMA) 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for high- Meets Multicarrier UMTS, cdma2000 , GSM performance wideband, single- and multicarrier transmit Spectral Masks (f = 122MHz) OUT applications. The device integrates a selectable 2x/4x/8x Noise Spectral Density = -160dBFS/Hz at interpolating filter, a digital quadrature modulator, and f = 16MHz OUT dual 16-bit, high-speed DACs on a single integrated cir- 90dBc SFDR at Low-IF Frequency (10MHz) cuit. At 30MHz output frequency and 500Msps update 88dBc SFDR at High-IF Frequency (50MHz) rate, the in-band SFDR is 81dBc, while only consuming 1.2W. The device also delivers 71dB ACLR for four- Low Power: 831mW (f = 250MHz) CLK carrier WCDMA at a 61.44MHz output frequency. User Programmable Selectable 2x, 4x, or 8x Interpolating Filters The selectable interpolating filters allow lower input data < 0.01dB Passband Ripple rates while taking advantage of the high DAC update > 95dB Stopband Rejection rates. These linear-phase interpolation filters ease recon- Selectable Real or Complex Modulator Operation struction filter requirements and enhance the passband Selectable Modulator LO Frequency: OFF, f / 2, IM dynamic performance. Each channel includes offset and or f / 4 IM gain programmability, allowing the user to calibrate out Selectable Output Filter: Lowpass or Highpass local oscillator (LO) feedthrough and sideband suppres- Per Channel Gain and Offset Adjustment sion errors generated by analog quadrature modulators. EV Kit Available (Order the MAX5898EVKIT) The MAX5898 features a f / 4 digital image-reject IM modulator. This modulator generates a quadrature-mod- Ordering Information ulated IF signal that can be presented to an analog I/Q PART TEMP RANGE PIN-PACKAGE modulator to complete the upconversion process. A second digital modulation mode allows the signal to be 68 QFN-EP* M AX5898E GK +D -40C to +85C frequency-translated with image pairs at f / 2 or f / 4. IM IM (10mm x 10mm) The MAX5898 features a standard LVDS interface for 68 QFN-EP* low electromagnetic interference (EMI). Interleaved M AX58 98E GK-D -40C to +85C (10mm x 10mm) data is applied through a single 16-bit bus. A 3.3V +Denotes a lead(Pb)-free/RoHS-compliant package. SPI port is provided for mode configuration. The pro- *EP = Exposed paddle. grammable modes include the selection of 2x/4x/8x D = Dry pack interpolating filters, f / 2, f / 4 or no digital quadra- IM IM ture modulation with image rejection, individual channel Selector Guide gain and offset adjustment, and offset binary or twos- RESOLUTION DAC UPDATE INPUT complement data interface. PART (BITS) RATE (Msps) LOGIC Compatible versions with CMOS interfaces and 12-, 14-, MAX5893 12 500 CMOS and 16-bit resolutions are also available. Refer to the MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14- MAX5894 14 500 CMOS bit CMOS, and the MAX5895 for 16-bit CMOS versions. MAX5895 16 500 CMOS MAX5898 16 500 LVDS Applications Base Stations: 3G Multicarrier UMTS, CDMA, and GSM Simplified Diagram Broadband Wireless Transmitters Broadband Cable Infrastructure OUTI DATA PORT DAC Instrumentation and Automatic Test Equipment (ATE) Analog Quadrature Modulation Architectures DATACLK DAC OUTQ SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications Industry Association. Pin Configuration appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLE16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs ABSOLUTE MAXIMUM RATINGS DV , AV to GND, DACREF ..................-0.3V to +2.16V DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA DD1.8 DD1.8 AV , AV , DV to GND, DACREF........-0.3V to +3.9V Continuous Power Dissipation (T = +70C) DD3.3 CLK DD3.3 A DATACLKP, DATACLKN, D0PD15P, 68-Pin QFN (derate 41.7mW/C above +70C) D0ND15N, SELIQP, SELIQN to GND, (Note 1) ...................................................................3333.3mW DACREF ..........................................-0.3V to (DV + 0.3V) Junction Temperature......................................................+150C DD1.8 CS, RESET, SCLK, DIN, DOUT to Operating Temperature Range ...........................-40C to +85C GND, DACREF ................................-0.3V to (DV + 0.3V) Storage Temperature Range .............................-65C to +150C DD3.3 CLKP, CLKN to GND, DACREF..............-0.3V to (AV + 0.3V) Lead Temperature (soldering, 10s) .................................+300C CLK REFIO, FSADJ to GND, DACREF ........-0.3V to (AV + 0.3V) Soldering Temperature (reflow) .......................................+260C DD3.3 OUTIP, OUTIN, OUTQP, OUTQN to GND, DACREF..................-1V to (AV + 0.3V) DD3.3 Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DV = AV = 1.8V, AV = AV = DV = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is DD1.8 DD1.8 CLK DD3.3 DD3.3 50 double-terminated, external reference at 1.25V, T = -40C to +85C, unless otherwise noted. Typical values are at T = +25C, A A unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 16 Bits Differential Nonlinearity DNL 1 LSB Integral Nonlinearity INL 3 LSB Offset Error OS -0.02 0.003 +0.02 %FS Offset Drift 0.03 ppm/C Gain Error GE (Note 3) -4 0.06 +4 %FS FS Gain-Error Drift 110 ppm/C Full-Scale Output Current I (Note 3) 2 20 mA OUTFS Output Compliance -0.5 +1.1 V Output Resistance R 1M OUT Output Capacitance C 5pF OUT DYNAMIC PERFORMANCE Maximum Clock Frequency f 500 MHz CLK Minimum Clock Frequency f 10 MHz CLK Maximum DAC Update Rate f f = f or f = f / 2 500 Msps DAC DAC CLK DAC CLK Minimum DAC Update Rate f f = f or f = f / 2 10 Msps DAC DAC CLK DAC CLK Maximum Data Clock Frequency f Interleaved data 250 MHz DATACLK Maximum Input Data Rate f Per channel 125 MWps DATA No interpolation -156 f = 125Mwps, DATA f = 16MHz, f 2x interpolation -157 OUT OFFSET = 10MHz, -12dBFS 4x interpolation -157 dBFS/ Noise Spectral Density Hz f = 125Mwps, DATA f = 16MHz, f 4x interpolation -154 OUT OFFSET = 10MHz, 0dBFS 2 MAX5898