EVALUATION KIT AVAILABLE Click here for production status of specific part numbers. MAX77752 Multichannel Integrated Power Management IC General Description Benefits and Features The MAX77752 is a highly-integrated power manage- Highly Integrated ment solution including three step-down converters, Three Buck Regulators a low-dropout linear regulator, two external regulators Integrated High-Accuracy Brownout enable outputs, two dedicated load switch controllers, Comparators and an inrush-current limiter which can be configured as One Low-Dropout Linear Regulator a third load switch controller using OTP. The MAX77752 Low-Input Voltage provides a combination of high-performance power Two Dedicated Load Switch Controllers management components, high-accuracy monitoring, One Inrush-Current Limiter, Configurable to be and a customized top-level controller that results in an Load Switch 3 Controller Using OTP efficient, size optimized solution. Two External Regulator Enable Outputs The 40-pin, 5mm x 5mm x 0.8mm, 0.4mm pitch TQFN Voltage Monitor for Backup Power Control package is ideal for space constrained applications. Highly Flexible and Configurable Numerous factory programmable options allow the device 2 I C-Compatible Interface to be tailored for many variations of the end application. Factory OTP Options Available Flexible Power Sequencer Applications Configurable Sleep-State Control Solid-State Drive Systems Small Size Handheld Devices 40-Pin, 5mm x 5mm x 0.8mm, 0.4mm Pitch TQFN Gaming Consoles 2 70mm Total Solution Size Drones Automation Systems Ordering Information appears at end of data sheet. Cameras Simplified Block Diagram VSYS RSENSE INR OUT SYS INB1 VSYS DC SOURCE VBUCK1 2.6V TO 5.5V 0.6V TO 2.194V OVERCURRENT LX1 2A MAX SENSOR BUCK1 PGND1 INB2 LSW3 DRIVER VSYS LSW DRV3 VBUCK2 (INRUSH 0.6V TO 2.194V LIMITER) LX2 FBLSW3 2A MAX VLSW3 BUCK2 PGND2 CENTRAL BIAS, INB3 GND VSYS TEMP SENSOR, VBUCK3 VOLTAGE 0.26V TO 1.52V LX3 MONITORS 3A MAX BUCK3 PGND3 LP MODE LP REQ VINLSW1 LP ACK LSW DRV1 LSW1 DRIVER PGOOD CENTRAL FBLSW1 VLSW1 RESET L LOGIC WP L SEQUENCER VINLSW2 EREG EN1 LOGIC I/O LSW DRV2 EREG EN2 LSW2 DRIVER REGISTERS FBLSW2 EREG POK VLSW2 AND DIGITAL INTERFACE IN LDO IN PHUP VSYS BLD IO VLDO 0.8V TO 3.96V OUT LDO SDA 0.15A MAX PMOS LDO SCL 19-100217 Rev 3 7/18MAX77752 Multichannel Integrated Power Management IC Absolute Maximum Ratings Top Buck IN DRV to GND .............................................-0.3V to +16.0V INB1, INB2, INB3 to SYS .................................-0.3V to +0.3V IN SNS to GND (Note 1) .................................-0.3V to +6.0V INB1 to PGND1 ................................................-0.3V to +6.0V INR OUT to GND .............................................-0.3V to +6.0V INB2 to PGND2 ................................................-0.3V to +6.0V SYS to GND .....................................................-0.3V to +6.0V INB3 to PGND3 ................................................-0.3V to +6.0V IN PHUP to GND .............................................-0.3V to +6.0V LX1 to PGND1 (Note 3).......................... -0.3V to V +0.3V INB1 RESET L to GND ....................................-0.3V to V +0.3V LX2 to PGND2 (Note 3).......................... -0.3V to V +0.3V SYS INB2 LP REQ to GND .....................................-0.3V to V +0.3V LX3 to PGND3 (Note 3).......................... -0.3V to V +0.3V SYS INB3 LP ACK to GND ......................................-0.3V to V +0.3V LX1, LX2 RMS Current per pin (T = +110C) SYS J LP MODE to GND ..................................-0.3V to V +0.3V (RMS current per pin (T = +110C)) ...............................1.7A SYS J WP L to GND (Note 2) ...................................-0.3V to V LX3 RMS Current per pin (T = +110C) H INT J (RMS current per pin (T = +110C)) ...............................3.0A PGOOD to GND (Note 2) ...............................-0.3V to V J H INT EREG EN1 to GND (Note 2) .........................-0.3V to V FBB1, FBB2, FBB3 to GND ....................-0.3V to V +0.3V H INT SYS PGND1, PGND2, PGND3 to GND ...................-0.3V to +0.3V EREG EN2 to GND ...........................................-0.3V to 6.0V EREG POK to GND ...............................-0.3V to V +0.3V 2 SYS I C BLD IO to GND (Note 2)..................................-0.3V to +6.0V SDA, SCL to GND ........................ -0.3V to V +0.3V IN VIO I2C WP L Sink Current .........................................................35mA SDA Sink Current ...........................................................35mA RESET L Sink Current ...................................................35mA Load Switch PGOOD Sink Current .....................................................35mA LSW DRV1 to GND .......................................-0.3V to +16.0V EREG EN1 Sink Current ...............................................35mA LSW DRV2 to GND .......................................-0.3V to +16.0V EREG EN2 Sink Current ...............................................35mA FBLSW1 to GND .....................................-0.3V to V +0.3V SYS LP REQ Sink Current ....................................................35mA FBLSW2 to GND .....................................-0.3V to V +0.3V SYS DGND to GND ..................................................-0.3V to +0.3V Continuous Power Dissipation (Multilayer Board) T = +70C, derate 35.70mW/C LDO A above +70C .............................................. mW to 2857.1mW IN LDO to GND................................................-0.3V to +6.0V Operating Temperature Range ........................... -40C to +85C OUT LDO to GND..............................-0.3V to V +0.3V IN LDO Junction Temperature ......................................................+150C Storage Temperature Range ............................ -40C to +150C Soldering Temperature (reflow) .......................................+260C Note 1: IN SNS voltage ramp rates greater than 2.8V/s trigger the internal ESD device and should be avoided. The ESD device recovers if exposed to an excessive ramp rate. Note 2: V is the maximum voltage of V and V . H INT SYS IN PHUP Note 3: The specified voltage limitation is for steady state conditions. Dead times of a few nano seconds exist during the dynamic BUCK regulator transitions from inductor charging to inductor discharging and vice versa. These dead times allow internal clamping diodes to PGNDx and INBx to forward bias (Vf~1V). When the LXx waveform is observed on a high-bandwidth oscil- loscope (100MHz), the LXx transition edges are commonly seen with 1.5V spikes. These spikes are due to (1) the internal clamping diode forward voltage and (2) the high rate of current change through the current loop s inductance (V = L x di/dt). Designs must follow the recommended printed circuit board (PCB) layout in order to minimize this current loop s inductance. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maxim Integrated 2 www.maximintegrated.com