Click here for production status of specific part numbers. MAX9111/MAX9113 Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 General Description Features The MAX9111/MAX9113 single/dual low-voltage differ- Low 300ps (max) Pulse Skew for High-Resolution ential signaling (LVDS) receivers are designed for high- Imaging and High-Speed Interconnect speed applications requiring minimum power consump- Space-Saving 8-Pin SOT23 and SO Packages tion, space, and noise. Both devices support switching Pin-Compatible Upgrades to DS90LV018A and rates exceeding 500Mbps while operating from a single DS90LV028A (SO Packages Only) +3.3V supply, and feature ultra-low 300ps (max) pulse Guaranteed 500Mbps Data Rate skew required for high-resolution imaging applications Low 29mW Power Dissipation at 3.3V such as laser printers and digital copiers. Conform to EIA/TIA-644 Standard The MAX9111 is a single LVDS receiver, and the MAX9113 Single +3.3V Supply is a dual LVDS receiver. Flow-Through Pinout Simplifies PCB Layout Both devices conform to the EIA/TIA-644 LVDS standard Fail-Safe Circuit Sets Output High for Undriven Inputs and convert LVDS to LVTTL/CMOS-compatible outputs. A fail-safe feature sets the outputs high when the inputs are High-Impedance LVDS Inputs when Powered Off undriven and open, terminated, or shorted. The MAX9111/ AEC-Q100 Qualified, Refer to Ordering Information MAX9113 are available in space-saving 8-pin SOT23 and for the Specific /V Versions SO packages. Refer to the MAX9110/MAX9112 data Typical Operating Circuit appears at end of data sheet. sheet for single/dual LVDS line drivers. Applications Laser Printers Network Switches/ Digital Copiers Routers Cellular Phone Base LCD Displays Stations Backplane Interconnect Telecom Switching Clock Distribution Equipment Automotive 19-1803 Rev 7 6/19MAX9111/MAX9113 Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 Absolute Maximum Ratings V to GND..............................................................-0.3V to +4V 8-Pin SO (derate 5.88mWC above +70C).................471mW CC IN to GND .........................................................-0.3V to +3.9V 8-Pin TDFN (derate 6.20mWC above +70C) ...........496mW OUT to GND..........................................-0.3V to (V + 0.3V) Operating Temperature Ranges CC ESD Protection All Pins MAX911 E.......................................................-40C to +85C (Human Body Model, IN +, IN -)...................................11kV MAX911 A .....................................................-40C to +125C Continuous Power Dissipation (T = +70C) Storage Temperature Range .............................-65C to +150C A 8-Pin SOT23 (derate 5.10mW/C above +70C) ...408.60mW Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information SOT23-8 PACKAGE CODE K8+1 Outline Number 21-0078 Land Pattern Number 90-0176 Thermal Resistance, Four-Layer Board: Junction to Ambient ( ) 195.80C/W JA Junction to Case ( ) 70C/W JC SO-8 PACKAGE CODE S8-2/S8+2 Outline Number 21-0041 Land Pattern Number 90-0096 Thermal Resistance, Single-Layer Board: Junction to Ambient ( ) 170C/W JA Junction to Case ( ) 40C/W JC Thermal Resistance, Four-Layer Board: Junction to Ambient ( ) 136C/W JA Junction to Case ( ) 38C/W JC TDFN-8 PACKAGE CODE T822CY+2 Outline Number 21-100341 Land Pattern Number 90-100117 Thermal Resistance, Four-Layer Board: Junction to Ambient ( ) 162C/W JA Junction to Case ( ) 20C/W JC For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a +, , or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Maxim Integrated 2 www.maximintegrated.com