MAX9171/MAX9172 19-2578 Rev 2 6/07 Single/Dual LVDS Line Receivers with In-Path Fail-Safe General Description Features The MAX9171/MAX9172 single/dual low-voltage differential Input Accepts LVDS and LVPECL signaling (LVDS) receivers are designed for high-speed In-Path Fail-Safe Circuit applications requiring minimum power consumption, Space-Saving 8-Pin TDFN and SOT23 Packages space, and noise. Both devices support switching rates exceeding 500Mbps while operating from a single 3.3V Fail-Safe Circuitry Sets Output High for Open, supply. Undriven Shorted, or Undriven Terminated Output The MAX9171 is a single LVDS receiver and the Flow-Through Pinout Simplifies PCB Layout MAX9172 is a dual LVDS receiver. Both devices con- Guaranteed 500Mbps Data Rate form to the ANSI TIA/EIA-644 LVDS standard and con- vert LVDS to LVTTL/LVCMOS-compatible outputs. A Second Source to DS90LV018A and DS90LV028A fail-safe feature sets the outputs high when the inputs (SO Packages Only) are undriven and open, terminated, or shorted. The Conforms to ANSI TIA/EIA-644 Standard MAX9171/MAX9172 are available in 8-pin SO packages 3.3V Supply Voltage and space-saving thin DFN and SOT23 packages. For lower skew devices, refer to the MAX9111/ MAX9113 -40C to +85C Operating Temperature Range data sheet. Low-Power Dissipation Applications Ordering Information Multipoint Backplane Interconnect TOP PKG PART PIN-PACKAGE MARK CODE Laser Printers MAX9171EKA-T 8 SOT23-8 AALX K8-1 Digital Copiers MAX9171ESA 8 SO S8-2 Cellular Phone Base Stations MAX9171ETA* 8 Thin DFN-EP** T833-2 LCD Displays MAX9172EKA-T 8 SOT23-8 AALY K8-1 Network Switches/Routers MAX9172ESA 8 SO S8-2 Clock Distribution MAX9172ETA* 8 Thin DFN-EP** T833-2 Note: All devices are specified over the -40C to +85C operating temperature range. *Future productcontact factory for availability. **EP = Exposed pad. T = Tape-and-reel. Pin Configurations MAX9171 MAX9171 MAX9172 MAX9172 V IN- 1 V 1 8 1 1 8 CC CC IN- IN1- 8 V V 8 IN1- CC CC IN+ 2 7 OUT GND 2 7 IN+ IN1+ 2 7 GND 2 7 IN1+ OUT1 N.C. 3 6 N.C. OUT 3 6 N.C. IN2+ 3 6 OUT1 3 6 IN2+ OUT2 N.C. GND IN2- OUT2 IN2- 4 5 N.C. 4 5 N.C. 4 5 GND 4 5 SO/TDFN* SOT23 SO/TDFN* SOT23 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.Single/Dual LVDS Line Receivers with In-Path Fail-Safe ABSOLUTE MAXIMUM RATINGS V to GND...........................................................-0.3V to +4.0V Operating Temperature Range ..........................-40C to +85C CC IN +, IN - to GND .................................................-0.3V to +4.0V Junction Temperature .....................................................+150C OUT to GND ............................................-0.3V to (V + 0.3V) Storage Temperature Range ............................-65C to +150C CC Continuous Power Dissipation (T = +70C) ESD Protection A 8-Pin SOT23 (derate 8.9mW/C above +70C) ...........714mW Human Body Model (IN +, IN -) ...................................13kV 8-Pin SO (derate 5.9mW/C above +70C) .................471mW Lead Temperature (soldering, 10s) ................................+300C 8-Pin TDFN (derate 24.4mW/C above +70C) ........1951mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V, differential input voltage V = 0.1V to 1.2V, receiver input voltage = 0 to V , common-mode voltage V = CC ID CC CM V /2 to (V - V /2 ), T = -40C to +85C, unless otherwise noted. Typical values are at V = 3.3V, V = 0.2V, V = 1.2V, ID CC ID A CC ID CM T = +25C.) (Notes 1, 2) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS INPUTS (IN +, IN -) Differential Input High Threshold V Figure 1 -40 0 mV TH Differential Input Low Threshold V Figure 1 -100 -40 mV TL Input Current (Noninverting Input) I Figure 1 +0.5 -2.1 -5.0 A IN+ Power-Off Input Current V = 0 to 3.6V, V = 0 to 3.6V, V = 0 IN+ IN- CC I -0.5 0 +0.5 A IN+OFF (Noninverting Input) or open (Figure 1) Input Current (Inverting Input) I Figure 1 -0.5 +4.4 +10.0 A IN- Power-Off Input Current V = 0 to 3.6V, V = 0 to 3.6V, V = 0 IN+ IN- CC I -0.5 0 +0.5 A IN-OFF (Inverting Input) or open (Figure 1) LVCMOS/LVTTL OUTPUTS (OUT ) Open, undriven short, or 2.7 3.2 undriven parallel termination Output High Voltage V I = -4.0mA V OH OH V = 0V 2.7 3.2 ID Output Low Voltage V I = 4.0mA, V = -100mV 0.1 0.4 V OL OL ID Output Short-Circuit Current I V = 0 (Note 3) -45 -77 -120 mA OS OUT POWER SUPPLY MAX9171 3.6 6 Supply Current I Inputs open mA CC MAX9172 7.0 9 2 MAX9171/MAX9172