PN-DESIGNKIT-39 Bourns

TISP9110LDM INTEGRATED COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION TISP9110LDM Overvoltage Protector High Performance Protection for SLICs with +ve and -ve Agency Recognition Battery Supplies Wide -110 V to +110 V Programming Range Description Low 5 mA max. Gate Triggering Current UL File Number: E215609 Dynamic Protection Performance Specified for International Surge Waveshapes 8-SOIC (210 mil) Package (Top View) Applications include: Wireless Local Loop (Tip or Ring) Line 1 8 NC Access Equipment Regenerated POTS Ground (-V ) G1 2 7 (BAT) VOIP Applications (+V ) G2 3 6 Ground (BAT) Rated for International Surge Wave Shapes (Ring or Tip) Line 45 NC I PPSM Wave Shape Standard A NC - No internal connection Terminal typical application names shown in 2/10 GR-1089-CORE 100 parenthesis 10/700ITU-T K.20/21/45 45 MD-8SOIC(210)-003-a 10/1000 GR-1089-CORE30 Device Symbol ................................................... UL Recognized Component Line Description The TISP9110LDM is a programmable overvoltage protection device designed to protect modern dual polarity supply rail ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the G1 G2 telephone line. Overvoltages can be caused by lightning, a.c. power contact and induction. Four separate protection structures are used two positive and two negative to provide optimum protection during Metallic (Differential) and Longitudinal (Common Mode) protection Ground conditions in both polarities. Dynamic protection performance is specified under typical international surge waveforms from Telcordia GR-1089-CORE, ITU-T K.44 and YD/T 950. The TISP9110LDM is programmed by connecting the G1 and G2 gate terminals to the negative (-V ) and positive (+V ) SLIC (BAT) (BAT) Battery supplies respectively. This creates a protector operating Line at typically +1.4 V above +V and -1.4 V below -V under (BAT) (BAT) SD-TISP9-001-a a.c. power induction and power contact conditions. The protector gate circuitry incorporates 4 separate buffer transistors designed to provide independent control for each protection element. The gate buffer transistors minimize supply regulation issues by reducing the gate current drawn to around 5 mA, while the high voltage base emitter structures eliminate the need for expensive reverse bias protection gate diodes. The TISP9110LDM is rated for common surges contained in regulatory requirements such as ITU-T K.20, K.45, Telcordia GR-1089-CORE, YD/T 950. By the use of appropriate overcurrent protection devices such as the Bourns Multifuse and Telefuse devices, circuits can be designed to comply with modern telecom standards. How To Order DevicePackage CarrierMOrder As arking CodeStandard Quantity TISP9110LDM 8-SOIC (210 mil) Embossed Tape Reeled TISP9110LDMR-S9110L 2000 AUGUST 2004 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. WARNING Cancer and Reproductive Harm The products described herein and this document are subject to specific legal disclaimers as set forth on the last www.P65Warnings.ca.gov page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP9110LDM Overvoltage Protector Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Repetitive peak off-state voltage V =0, V +5 V V -120 V G1(Line) G2 DRM V =0, V -5 V +120 G2(Line) G1 Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4) 100 2/10 s (Telcordia GR-1089-CORE) I 45 A 5/310 s (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 s) PPSM 30 10/1000 s (Telcordia GR-1089-CORE) Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5) 9.0 0.2 s I 5.0 A 1 s TSM 1.7 900 s Maximum negative battery supply voltage V -110 V G1M Maximum positive battery supply voltage V +110 V G2M Maximum differential battery supply voltage V 220 V (BAT)M Junction temperature T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. Initially the device must be in thermal equilibrium with T = 25 C. The surge may be repeated after the device returns to its initial J conditions. 2. The rated current values may be applied to either of the Line to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of a single terminal pair). 3. Rated currents only apply if pins 6 & 7 (Ground) are connected together. 4. Applies for the following bias conditions: V = -20 V to -110 V, V = 0 V to +110 V. G1 G2 5. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Electrical Characteristics for any Section, T = 25 C (Unless Otherwise Noted) A Parameter Test Conditions Min Typ Max Unit T = 25 C -5 A V = V , V = 0, V +5 V D DRM G1(Line) G2 T = 85 C -50 A I Off-state current A D T = 25 C +5 A V = V , V = 0, V -5 V D DRM G2(Line) G1 T = 85 C +50 A I Negative-gate leakage current V = -220 V -5 A G1(Line) G1(Line) I Positive-gate leakage current V = +220 V +5 A G2(Line) G2(Line) V = -100 V, I = -100 A (see Note 6) 2/10 s -15 G1 T V Gate - Line impulse breakover voltage V G1L(BO) V = -100 V, I = -30 A 10/1000 s -11 G1 T V = +100 V, I = +100 A (see Note 6) 2/10 s +15 G2 T V Gate - Line impulse breakover voltage V G2L(BO) V = +100 V, I = +30 A 10/1000 s +11 G2 T I - Negative holding current V = -60 V, I = -1 A, di/dt = 1 A/ms -150 mA H G1 T I Negative-gate trigger current I =-5A, t 20 s, V = -60 V +5 mA G1T T p(g) G1 , I Positive-gate trigger current I =5A t 20 s, V = 60 V -5 mA G2T T p(g) G2 C Line - Ground off-state capacitance f = 1 MHz, V = -3 V, G1 & G2 open circuit 32 pF O D NOTE: 6. Voltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise. AUGUST 2004 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.