TISP4A265H3BJ ASYMMETRICAL BIDIRECTIONAL THYRISTOR SPD TISP4A265H3BJ LCAS R Protector LINE Agency Recognition RING Line Protection for: -LCAS (Line Card Access Switch) Description -ADSL Interfaces UL File Number: E215609 Voltages Optimized for: -Battery-Backed Ringing Circuits Maximum Ringing a.c...........................................90 V rms SMB Package (Top View) Maximum Battery Voltage ............................................-52 V -ADSL Voltage ...........................................................23 V peak -Minimum Ambient Temperature ....................................... 0 C MT1 12 MT2 V V DRM (BO) Device V V MD4A265 +100 +125 4A265 -200 -265 Device Symbol Rated for International Surge Wave Shapes MT2 I TSP Wave Shape Standard A 2/10 s GR-1089-CORE 500 8/20 s IEC 61000-4-5 300 10/160 s TIA/EIA-IS-968 250 MT1 10/700 s ITU-T K.20/45/21 200 SD4XAN 10/560 s TIA/EIA-IS-968 160 10/1000 s GR-1089-CORE 100 .................................................UL Recognized Component Description The TISP4A265H3BJ is an asymmetrical bidirectional overvoltage protector. It is designed to limit the peak voltages on the ring line terminal of the 7581/2/3 LCAS (Line Card Access Switches). The TISP4A265H3BJ must be connected with bar-indexed terminal 1, MT1, to the protective ground and terminal 2, MT2, to the ring conductor. The TISP4A265H3BJ voltages are chosen to give adequate LCAS ring line terminal protection for all switch conditions. The most potentially stressful condition is low level power cross when the LCAS switches are closed. Under this condition, the TISP4A265H3BJ limits the voltage and corresponding LCAS dissipation until the LCAS thermal trip operates and opens the switches. Under open-circuit ringing conditions, the line ring conductor will have high peak voltages. For battery backed ringing, the ring conductor will have a larger peak negative voltage than positive, i.e. the peak voltages are asymmetric. The TISP4A265H3BJ has a similar voltage asymmetry and will allow the maximum possible ringing voltage, while giving the most effective pr otection. On a connected line, the tip conductor will have much smaller voltage levels than the open-circuit ring conductor values. Here a TISP4xxxH3BJ series, symmetrical voltage protector gives adequate protection. Overvoltages are initially clipped by breakdown clamping. If sufficient current is available from the overvoltage, the breakdown voltage will rise to the breakover level, which causes the device to switch into a low-voltage on-state condition. This switching action removes the high voltage stress from the following circuitry and causes the current resulting from the overvoltage to be safely diverted through the protector. The high holding (switch off) current helps prevent d.c. latchup as the diverted current subsides. How to Order Device PackageCarrier Order As TISP4A265H3BJ BJ (J-Bend DO-214AA/SMB)R (Embossed Tape Reeled) TISP4A265H3BJR-S JANUARY 2002 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. WARNING Cancer and Reproductive Harm The products described herein and this document are subject to specific legal disclaimers as set forth on the last www.P65Warnings.ca.gov page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP4A265H3BJ LCAS R Protector LINE Description (Continued) The TISP4A265H3BJ is guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. This high (H) current protection device is in a plastic SMBJ package (JEDEC DO-214AA with J-bend leads) and supplied in embossed carrier reel pack. For alternative voltage and holding current values, consult the factory. Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit +100 Repetitive peak off-state voltage, (see Note 1) V V DRM -200 Non-repetitive peak on-state pulse current (see Notes 2, 3 and 4) 2/10 s (GR-1089-CORE, 2/10 s voltage wave shape) 500 8/20 s (IEC 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 300 10/160 s (TIA/EIA-IS-968 (Replaces FCC Part 68), 10/160 s voltage wave shape) 250 I A TSP 5/310 s (ITU-T K.44, 10/700 s voltage wave shape used in K.20/45/21) 200 5/320 s (TIA/EIA-IS-968 (Replaces FCC Part 68), 9/720 s voltage wave shape) 200 10/560 s (TIA/EIA-IS-968 (Replaces FCC Part 68), 10/560 s voltage wave shape) 160 10/1000 s (GR-1089-CORE, 10/1000 s voltage wave shape) 100 Non-repetitive peak on-state current (see Notes 2, 3 and 5) 20 ms (50 Hz) full sine wave 55 16.7 ms (60 Hz) full sine wave I 60 A TSM 1000 s 50 Hz/60 Hz a.c. 2.2 Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A di /dt 400 A/s T Junction temperature T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. See Figure 7 for voltage values at other temperatures. 2. Initially, the TISP4A265H3BJ must be in thermal equilibrium with T = 25 C. J 3. The surge may be repeated after the TISP4A265H3BJ returns to its initial conditions. 4. See Figure 8 for current ratings at other temperatures. 5. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track widths. See Figure 6 for the current ratings at other durations. Derate current values at -0.61 %/C for ambient temperatures above 25 C. Overload Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Maximum overload on-state current without open circuit, 50 Hz/60 Hz a.c. (see Note 6) 0.03 s 60 0.07 s 40 I A rms T(OV)M 1.6 s 8 5.0 s 7 1000 s 2.2 NOTE 6: Peak overload on-state current during a.c. p ower cross tests of GR-1089-CORE and UL 1950/60950. T hese electrical stress levels may damage the TISP4A265H3BJ silicon chip. After test, the pass criterion is either that the device is functional or, if it is faulty, that it has a short circuit fault mode. In the short circuit fault mode, the following equipment is protected as the device is a permanent short across the line. The equipment would be unprotected if an open circuit fault mode developed. JANUARY 2002 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.