TISP4A270H3BJ ASYMMETRICAL-BIDIRECTIONAL THYRISTOR SPD TISP4A270H3BJ LCAS R Protector LINE Optimized LCAS R Protector LINE SMB Package (Top View) TISP4A270H3BJ V Derived from: (BO) -Break Switch, SW1 & SW2, Ratings -Ring Return Switch, SW3, Rating 12 G R -Ringing Access Switch, SW4, Rating -Switch Isolation Ratings -Battery Voltage Range of -40 V to -60 V MD4A270B -Power Fault Conditions -Lightning Impulse Conditions -LCAS Characteristic Temperature Range Device Symbol and Circuit Application TISP4A270H3BJ Designed for: SW1 7581 LCAS -Battery-Backed Ringing Circuits Break Voltage Swing +148 V to -206 V switch TISP4165H3 Allows .103 V rms Ringing with -60 V Battery TIP Temperature Range -40 C to +85 C T T LINE BAT SW3 V V F DRM (BO) GND Ring Device return V V switch G +160 +217 SW2 V BAT 4A270 Break -222 -270 switch R R R LINE BAT Rated for International Surge Wave Shapes RING V DD I TISP4A270H3 PPSM SW4 Wave Shape Standard LATCH Ringing A access INPUT 2/10 GR-1089-CORE 500 switch D 10/700 ITU-T K.20/45/21 150 GND 10/1000 GR-1089-CORE 100 T T R RINGING SD RINGING AI4BITAMA .......................................UL Recognized Component Description The TISP4A270H3BJ is an asymmetrical-bidirectional thyristor surge protective device (SPD). It is designed to limit the peak voltages on the R (Ring Line) terminal of 7581/2/3 LCAS (Line Card Access Switch) devices. The TISP4A270H3BJ must have the bar-indexed LINE terminal 1 (G) connected to the protective ground and terminal 2 (R) connected to the R terminal. LINE The TISP4A270H3BJ voltages are chosen to give R terminal protection for all LCAS switch conditions. The most potentially stressful LINE condition is low level power cross when the switches are closed. Under this condition, the TISP4A270H3BJ limits the voltage and corresponding LCAS dissipation until the LCAS thermal trip operates and opens the switches. Under open-circuit ringing conditions, the R terminal will have high peak voltages. For battery backed ringing, the R terminal will LINE LINE have a larger peak negative voltage than positive, i.e. the peak voltages are asymmetric. The TISP4A270H3BJ has a similar voltage asymmetry which will allow the maximum possible ringing voltage, while still giving protection. With a connected telephone line, the LCAS T (Tip Line) terminal voltage levels will be less than 50 % of the open-circuit R terminal values. So the T terminal can be LINE LINE LINE protected by a symmetrical-bidirectional overvoltage protector of the TISP4xxxH3BJ series. How To Order Device Package Carrier Order As TISP4A270H3BJ BJ (SMB/DO-214AA with J-Bend) R (Embossed Tape Reeled) TISP4A270H3BJR-S *RoHS Directive 2002/95/EC Jan 27 2003 including Annex APRIL 2002 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. *RoHS COMPLIANT Control SCR, Diode logic protectionTISP4A270H3BJ LCAS R Protector LINE Description (Continued) These devices allow signal voltages up to the maximum off-state voltage value, V , see Figure 1. Voltages above V are clipped and DRM DRM will not exceed the breakover voltage, V , level. If sufficient current flows due to the overvoltage, the device switches into a low-voltage (BO) on-state condition, which diverts the current from the overvoltage though the device. When the diverted current falls below the holding current, I , level the devices switches off and restores normal system operation. H The TISP4A270H3BJ is guaranteed to voltage limit and withstand the listed international lightning surges in both polarities. This high current protection device is in a plastic SMB package (JEDEC DO-214AA) and supplied in embossed tape reel pack. Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit T = 25 C +160/-222 A Repetitive peak off-state voltage, (see Note 1) V V DRM T = -40 C 148/-206 A Non-repetitive peak on-state pulse current (see Notes 2 and 3) 2/10 (GR-1089-CORE, 2/10 voltage wave shape) 500 I A PPSM 5/310 (ITU-T K.44, 10/700 s voltage wave shape used in K.20/45/21) 150 10/1000 (GR-1089-CORE, 10/1000 voltage wave shape) 100 Non-repetitive peak on-state current (see Notes 2, 3 and 4) 20 ms (50 Hz) full sine wave 55 16.7 ms (60 Hz) full sine wave I 60 A TSM 1000 s 50 Hz/60 Hz a.c. 2.2 Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A di /dt 400 A/s T Junction temperature T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. See Figure 7 for voltage values at intermediate temperatures. 2. Initially, the TISP4A270H3BJ must be in thermal equilibrium with T = 25 C. J 3. The surge may be repeated after the TISP4A270H3BJ returns to its initial conditions. 4. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track widths. See Figure 6 for the current ratings at other durations. Derate current values at -0.61 %/C for ambient temperatures above 25 C. Overload Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Maxima um overload on-state current without open circuit, 50 Hz/60 Hz a.c. (see Note 5) 0.03 s 60 0.07 s 40 I A rms T(OV)M 1.6 s 8 5.0 s 7 1000 s 2.2 NOTE 5: Peak overload on-state current during a.c. power cross tests of GR-1089-CORE and UL 1950/60950. These electrical stress levels may damage the TISP4A270H3BJ silicon chip. After test, the pass criterion is either that the device is functional or, if it is faulty, that it has a short circuit fault mode. In the short circuit fault mode, the following equipment is protected as the device is a permanent short across the line. The equipment would be unprotected if an open circuit fault mode developed. APRIL 2002 - REVISED JANUARY 2007 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.