TISP61089HDM DUAL FORWARD-CONDUCTING P-GATE THYRISTOR PROGRAMMABLE OVERVOLTAGE PROTECTOR TISP61089HDM Overvoltage Protector Intended for Use in GR-1089-CORE Issue 3 Compliant Additional Information Line Cards Click these links for more information: Dual, Voltage-Programmable SLIC Protector Low 15 mA max. Gate Triggering Current Supports Battery Voltages Down to -155 V High 150 mA min. Holding Current PRODUCT TECHNICAL INVENTORY SAMPLES CONTACT LIBRARY Rated for GR-1089-CORE Issue 3 Conditions GR-1089-CORE Test I Agency Recognition PPSM Impulse Waveshape Section Test A Description 4.6.7 4 2/10 500 4.6.8 1 UL File Number: E215609 4.6.7 1, 3 10/1000 100 4.6.7.1 1 8-SOIC (210 mil) Package (Top View) Meets GR-1089-CORE First Level A.C. Power Fault Conditions K1 (Tip) (Tip) K1 1 8 GR-1089-CORE I RMS Power Fault Duration (Ground) G A Section 4.6.10 (Gate) 2 7 As Test NC 3 6 A (Ground) 10.33 900 K2 K2 (Ring) (Ring) 45 20.17 900 31 1 NC - No internal connection 41 1 Terminal typical application names shown in 60.5 30 parenthesis MD-8SOIC(210)-001-b 72.2 2 83 1.1 Device Symbol 95 0.4 K1 K1 GR-1089-CORE Second Level A.C. Power Fault Conditions are Detailed in the Applications Information Section A ................................................... UL Recognized Component G A K2 K2 The negative protection voltage is controlled by the voltage, V , GG applied to the G terminal. SD-TISP6-001-a How To Order DevicePackage CarrierMOrder As arking CodeStandard Quantity TISP61089HDM 8-SOIC (210 mil) Embossed Tape Reeled TISP61089HDMR-S 61089H 2000 MAY 2004 REVISED NOVEMBER 2021 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their WARNING Cancer and Reproductive Harm specific applications. The products described herein and this document are subject to specific legal disclaimers as www.P65Warnings.ca.gov set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP61089HDM Overvoltage Protector Description The TISP61089HDM is a dual forward-conducting buffered p-gate thyristor (SCR) overvoltage protector. It is designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The TISP61089HDM limits voltages that exceed the SLIC supply rail voltage. The TISP61089HDM parameters are specified to allow equipment compliance with Telcordia GR-1089-CORE, Issue 3 and ITU-T recommendations K.20, K.21 and K.45. The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of -20 V to -155 V. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. The protection voltage will then track the negative supply voltage and the overvoltage stress on the SLIC is minimized. Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state condition. As the overvoltage subsides the high holding current of TISP61089HDM SCR helps prevent d.c. latchup. The TISP61089HDM is designed to be used with a pair of Bourns SF-3812TM125T-2 SinglFuse Telefuse Telecom Protectors for overcurrent protection. Level 2 power fault compliance requires the series overcurrent element to become open-circuit or high impedance. For equipment compliant to ITU-T recommendations K.20, K.21 or K.45 only, the series resistor value is set by the coordination requirements. For coordination with a 400 V limit GDT, a minimum series resistor value of 6.5 is recommended. Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Repetitive peak off-state voltage, V =0 V -170 V GK DRM =0 V -167 V Repetitive peak gate-cathode voltage, V KA GKRM Non-repetitive peak impulse current (see Notes 1, 2 and 3) 100 10/1000 s (Telcordia GR-1089-CORE, Issue 3) 150 5/310 s (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 s) I 100 A 10/360 s (Telcordia GR-1089-CORE, Issue 3) PPSM 500 1.2/50 s voltage waveshape (Telcordia GR-1089-CORE, Issue 3), including 3 non-inductive r esistor 500 2/10 s (Telcordia GR-1089-CORE, Issue 3) Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 4) 7.7 0.5 s 6.1 1 s 4.8 2 s I A TSM 3.7 5 s 2.8 30 s 2.6 900 s Junction temperatur e T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. Initially the device must be in thermal equilibrium with T = 25 C. The surge may be repeated after the device returns to its initial J conditions. 2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. A dditionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Ratings are obtained by using the gate circuitry as shown in Fig. 3. 3. Rated currents only apply if pins 1 & 8 (Tip) are connected together, pins 4 & 5 (Ring) are connected together a nd pins 6 & 7 (Anode) are connected together. 4. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. MAY 2004 REVISED NOVEMBER 2021 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.