TISP61089Q PROGRAMMABLE OVERVOLTAGE PROTECTOR QUAD FORWARD-CONDUCTING P-GATE THYRISTOR TISP61089Q SLIC Overvoltage Protector Quad Voltage-Programmable Protector D Package (Top View) - Wide -20 V to -155 V Programming Range - Low 5 mA max. Gate Triggering Current K1 1 8 K2 - High 150 mA min. Holding Current G1,G2 2 7 A 10/700 Protection Voltage Speci ed A G3,G4 3 6 K4 K3 45 Protection Level MDRXAN Element 40 A, 10/700 Diode +12 Device Symbol Crowbar -64 K1 V = -48 V GG Rated for ITU-T and YD/T-950 10/700 impulses Also rated for Telcordia Intra-building impulses G1,G2 Description The TISP61089Q is a quad forward-conducting buffered p-gate K2 overvoltage protector. It is designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the tele- A phone line caused by lightning, a.c. power contact and induction. The A TISP61089Q limits voltages that exceed the SLIC supply rail voltage. The TISP61089Q parameters are speci ed to allow equipment compliance K3 with Bellcore GR-1089-CORE, ITU-T K.20, K.21 and K.45 and YD/T-950. The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of -20 V to -75 V. The protector gate is connected to this negative supply. This references the protection G3,G4 (clipping) voltage to the negative supply voltage. As the protection voltage will then track the negative supply voltage the overvoltage stress on the SLIC is minimized. SDRXAIA Positive overvoltages are clipped to ground by diode forward conduction. K4 Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If suf cient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the overvoltage subsides, the high holding current of the crowbar prevents d.c. latchup. The TISP61089Q is intended to be used with a series combination of a 25 or higher resistance and a suitable overcurrent protector. Power fault compliance requires the series overcurrent element to open-circuit or become high impedance (see Applications Information). For equipment compliant to ITU-T recommendations K.20 or K.21 only, the recommended 10 series resistor value is set by the power cross requirements. These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high reliability and are virtually transparent in normal operation. The TISP61089Q buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The TISP61089Q is available in an 8-pin plastic small-outline surface mount package. How to Order Device Package Carrier Order As Marking Code Standard Quantity TISP61089Q 8 Pin Small Outline (D008) Embossed Tape Reeled TISP61089QDR-S 1089Q 2500 *RoHS Directive 2002/95/EC Jan 27 2003 including Annex JULY 2010 Speci cations are subject to change without notice. Customers should verify actual device performance in their speci c applications. *RoHS COMPLIANT TISP61089Q SLIC Overvoltage Protector Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) J Rating Symbol Value Unit Repetitive peak off-state voltage, I = 0 -40 C T 85 C V -170 V G J DRM Repetitive peak gate-cathode voltage, V = 0 -40 C T 85 C V -167 KA J GKRM Non-repetitive peak on-state pulse current (see Notes 1 and 2) 30 10/1000 s (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) I A TSP 40 5/320 (ITU-T K.20/21/45, YD/T-950, open circuit voltage waveshape 10/700) 120 2/10 (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) Non-repetitive peak on-state current, 60 Hz (see Notes 1, 2 and 3) I A TSM 0.5 900 s Non-repetitive peak gate current, 2/10 s pulse, cathodes commoned (see Notes 1 and 2) I 40 A GSM Junction temperature T -40 to +150 C J Storage temperature range T -40 to +150 C stg NOTES: 1. Initially the protector must be in thermal equilibrium with T = 25 C. The surge may be repeated after the device returns to its initial J conditions. 2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied to any cathode- anode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in this case the anode terminal current will be four times the rated current value of an individual terminal pair). 3. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Recommended Operating Conditions Min Typ Max Unit C Gate decoupling capacitor 100 nF G TISP61089Q series resistor for first-level and second-level surge survival 40 R S TISP61089Q series resistor for first-level surge survival 25 Electrical Characteristics, T = 25 C (Unless Otherwise Noted) J Parameter Test Conditions Min Typ Max Unit I Off-state current V = V , V = 0 -5 A D D DRM GK V Breakover voltage 10/700 s, I = -40 A, R = 55 , V = -48 V, C = 100nF -64 V (BO) T S GG G V Forward voltage I = 5 A, t = 200 s 3V F F w Peak forward recovery V 10/700 s, I = 40 A, R = 55 , V = -48 V, C = 100nF 12 V FRM F S GG G voltage I Holding current I =-1A, di/dt=1A/ms, V = -100 V -150 mA H T GG I Gate reverse current V =V = V , V = 0 -5 A GAS GG GK GKRM KA I Gate trigger current I = 3 A, t 20 s, V = -100 V 5 mA GT T p(g) GG V Gate trigger voltage I = 3 A, t 20 s, V = -100 V 2.5 V GT T p(g) GG V = -3V 100 Anode-cathode off-state D C f = 1 MHz, V = 1 V I = 0, (see Note 4) pF AK d G capacitance V = -48V 50 D JULY 2010 Speci cations are subject to change without notice. Customers should verify actual device performance in their speci c applications.