SILICON POWER MOS FET NE5520279A 3.2 V OPERATION SILICON RF POWER LDMOS FET FOR 1.8 GHz 1.6 W TRANSMISSION AMPLIFIERS DESCRIPTION The NE5520279A is an N-channel silicon power laterally diffused MOS FET specially designed as the transmission power amplifier for 3.2 V DCS1800 handsets. Dies are manufactured using our NEWMOS2 technology (our WSi gate laterally diffused MOS FET) and housed in a surface mount package. This device can deliver 32.0 dBm output power with 45% power added efficiency at 1.8 GHz under the 3.2 V supply voltage. FEATURES High output power : Pout = 32.0 dBm TYP. (VDS = 3.2 V, IDset = 700 mA, f = 1.8 GHz, Pin = 25 dBm) High power added efficiency : add = 45% TYP. (VDS = 3.2 V, IDset = 700 mA, f = 1.8 GHz, Pin = 25 dBm) High linear gain : GL = 10 dB TYP. (VDS = 3.2 V, IDset = 700 mA, f = 1.8 GHz, Pin = 5 dBm) Surface mount package : 5.7 5.7 1.1 mm MAX. Single supply : VDS = 2.8 to 6.0 V APPLICATION Digital cellular phones : 3.2 V DCS1800 Handsets ORDERING INFORMATION Part Number Package Marking Supplying Form NE5520279A-T1 79A A2 12 mm wide embossed taping Gate pin face the perforation side of the tape Qty 1 kpcs/reel NE5520279A-T1A 12 mm wide embossed taping Gate pin face the perforation side of the tape Qty 5 kpcs/reel Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: NE5520279A-A Caution: Observe precautions when handling because these devices are sensitive to electrostatic discharge Document No. PU10123EJ03V0DS (3rd edition) The mark shows major revised points. Date Published July 2003 CP(K) DISCONTINUEDNE5520279A ABSOLUTE MAXIMUM RATINGS (TA = +25C) Parameter Symbol Ratings Unit Drain to Source Voltage VDS 15.0 V Gate to Source Voltage VGS 5.0 V Drain Current ID 0.6 A Note Drain Current (Pulse Test) ID 1.2 A Total Power Dissipation Ptot 12.5 W Channel Temperature Tch 125 C Storage Temperature Tstg 55 to +125 C Note Duty Cycle 50%, Ton 1 s RECOMMENDED OPERATING CONDITIONS Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Drain to Source Voltage VDS 2.8 3.0 6.0 V Gate to Source Voltage VGS 0 2.0 3.0 V Drain Current ID Duty Cycle 50%, Ton 1 s 800 1 000 mA Input Power Pin f = 1.8 GHz, VDS = 3.2 V 24 25 30 dBm ELECTRICAL CHARACTERISTICS (TA = +25C, unless otherwise specified, using NEC standard test fixture) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Gate to Source Leak Current IGSS VGS = 5.0 V 100 nA Drain to Source Leakage Current IDSS VDS = 6.0 V 100 nA (Zero Gate Voltage Drain Current) Gate Threshold Voltage Vth VDS = 3.5 V, ID = 1 mA 1.0 1.4 1.9 V Thermal Resistance Rth Channel to Case 8 C/W Transconductance Gm VDS = 3.2 V, ID = 700 mA 1.3 S Drain to Source Breakdown Voltage BVDSS IDSS = 10 A 15 18 V Output Power Pout f = 1.8 GHz, VDS = 3.2 V, 30.5 32.0 dBm mA Drain Current ID Pin = 25 dBm, 800 Power Added Efficiency add IDset = 700 mA (RF OFF), Note1 40 45 % Note2 10 dB Linear Gain GL Notes 1. DC performance is 100% testing. RF performance is testing several samples per wafer. Wafer rejection criteria for standard devices is 1 reject for several samples. 2. Pin = 5 dBm 2 Data Sheet PU10123EJ03V0DS DISCONTINUED