THC63LVDM87 CEL

THC63LVDM87 Rev.1.00 E THC63LVDM87 LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER General Description Features The THC63LVDM87 transmitter is designed to support Low power 1.8V CMOS design pixel data transmission between Host and Flat Panel 5mm x 5mm/49pin/0.65mm pitch VFBGA Package Display up to 1080p/WUXGA resolutions. applicable to non-HDI PCB The THC63LVDM87 converts 28bits of CMOS/TTL Wide dot clock range, 8-160MHz suited for data into LVDS(Low Voltage Differential Signaling) TV Signal: NTSC(12.27MHz) - 1080p(148.5MHz) data stream. The transmitter can be programmed for ris- PC Signal: QVGA(8MHz) - WUXGA(154MHz) ing edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 160MHz, 24bits of Supports 1.8V single power supply RGB data and 4bits of timing and control data 1.8V/2.5V/3.3V CMOS inputs are supported by (HSYNC, VSYNC, DE, CONT1) are transmitted at an setting IOVCC=1.8V/2.5V/3.3V effective rate of 1120Mbps per LVDS channel. LVDS swing is reducible by RS-pin to reduce EMI and power consumption PLL requires no external components Supports spread spectrum clock generator On chip jitter filtering Power down mode Input clock triggering edge is selectable by R/F-pin Block Diagram THC63LVDM87 TTL/CMOS LVDS Inputs Outputs 7 TA0-6 TA +/- 7 TB0-6 TB +/- 7 TC0-6 TC +/- 7 TD0-6 TD +/- (56-1120Mbit/On Each LVDS Channel) TRANSMITTER CLKIN TCLK +/- PLL (8 to 160MHz) CLOCK R/F (LVDS) 8-160MHz /PDWN RS Copyright2012 THine Electronics, Inc. 1/12 THine Electronics, Inc. TTL PARALLEL TO SERIALTHC63LVDM87 Rev.1.00 E Pin Out Copyright2012 THine Electronics, Inc. 2/12 THine Electronics, Inc.