CDB42448 Cirrus Logic

Clocks/Data CDB42448 Evaluation Board For CS42448 Features Description The CDB42448 evaluation board is an excellent means z Single-ended/Single-ended to Differential for evaluating the CS42448 CODEC. Evaluation re- Analog Inputs quires an analog/digital signal source and analyzer, and z Single-ended/Differential to Single-ended power supplies. A Windows PC compatible computer Analog Outputs must be used to evaluate the CS42448. z CS8406 S/PDIF Digital Audio Transmitter System timing for the IS, Left-Justified and Right-Justi- z CS8416 S/PDIF Digital Audio Receiver fied interface formats can be provided by the CS42448, z Header for Optional External Software by the CS8416, or by a DSP I/O stake header with a DSP connected. System timing for TDM mode is provided by Configuration of CS42448 an FPGA using clocks derived from the CS8416 or DSP z Header for External DSP Serial Audio I/O I/O header. z 3.3 V Logic Interface RCA phono jacks are provided for the CS42448 analog z Pre-defined Software Scripts inputs and outputs. Digital data I/O is available via RCA z S/PDIF-to-TDM Conversion for Easy phono or optical connectors to the CS8416 and CS8406. Evaluation of the TDM Digital Interface The Windows software provides a GUI to make config- z Demonstrates Recommended Layout and uration of the CDB42448 easy. The software Grounding Arrangements communicates through the PCs serial port to configure z Windows Compatible Software Interface to the control port registers so that all features of the Configure CS42448 and Inter-board CS42448 can be evaluated. The evaluation board may also be configured to accept external timing and data Connections signals for operation in a user application during system ORDERING INFORMATION development. CDB42448 Evaluation Board I Serial Control Port CS8406 S/PDIF 2 ANALOG INPUT I C/SPI Header Output y Single-Ended to Differential Input y Single-Ended Input MCLK BUS CS42448 ADC/DAC Clocks/ ANALOG OUTPUT Data CS8416 y Differential to Hardware S/PDIF Single-Ended Setup Input Output FPGA Clocks /Data y Single-Ended Output Osc. AUXILIARY ANALOG INPUT y Single-Ended MCLK Divided CS5341 DSP HEADER Input Cirrus Logic, Inc. Copyright Cirrus Logic, Inc. 2004 www.cirrus.com OCT 04 (All Rights Reserved) DS648DB2 ADC/DAC Clocks & DataCDB42448 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 FPGA ................................................................................................................................. 4 1.4 CS42448 Audio CODEC .................................................................................................... 4 1.5 CS8406 Digital Audio Transmitter ...................................................................................... 4 1.6 CS8416 Digital Audio Receiver .......................................................................................... 5 1.7 CS5341 .............................................................................................................................. 5 1.8 Canned Oscillator .............................................................................................................. 5 1.9 External Control Headers ...................................................................................................5 1.10 Analog Input ..................................................................................................................... 6 1.11 Analog Outputs ................................................................................................................ 6 1.12 Serial Control Port ............................................................................................................ 6 1.13 USB Control Port ............................................................................................................. 6 2. SOFTWARE MODE .................................................................................................................. 7 2.1 Advanced Register Debug Tab .......................................................................................... 7 3. FPGA SYSTEM OVERVIEW .................................................................................................... 9 3.1 FPGA Setup ....................................................................................................................... 9 3.1.1 S/PDIF In, S/PDIF Out (SPDIF1-4) .......................................................................9 3.1.2 Analog In, Analog Out (Digital Loopback) ............................................................. 9 3.1.3 DSP Routing ......................................................................................................... 9 3.2. Internal Sub-Clock Routing ............................................................................................. 10 3.3. Internal Data Routing ...................................................................................................... 11 3.4. Internal TDM Conversion, MUXing and Control (TDMer) ............................................... 12 3.5 External MCLK Control .................................................................................................... 13 3.5.1 CS5341 MCLK .................................................................................................... 13 3.5.2 TDMer MCLK ...................................................................................................... 13 3.6 Bypass Control - Advanced ............................................................................................. 14 4. FPGA REGISTER QUICK REFERENCE ............................................................................... 15 5. FPGA REGISTER DESCRIPTION ......................................................................................... 16 6. CDB CONNECTORS AND JUMPERS ................................................................................... 28 7. CDB BLOCK DIAGRAM ................................................................................................... 30 8. CDB SCHEMATICS ............................................................................................................. 31 9. CDB LAYOUT ..................................................................................................................... 41 10. REVISION HISTORY ............................................................................................................ 44 2 DS648DB2