CDB42L55 Cirrus Logic

CDB42L55 Evaluation Board for CS42L55 Features Description The CDB42L55 is the ideal evaluation platform solution to test Line-level Analog Inputs and evaluate the CS42L55.The CS42L55 is a highly integrat- 4 RCA Input Jacks ed, 24-bit, ultra-low-power stereo CODEC based on multi-bit Delta-Sigma modulation suitable for low-power portable sys- Line-Level & HP Analog Output tem applications. Use of the board requires an analog or digi- Stereo Headphone Out Jack tal signal source, an analyzer, and power supplies. A RCA Audio Jacks for Headphone and Line Windows PC-compatible computer is also needed in order to Outputs configure the CS42L55 and the board. S/PDIF Interface System timing can be provided by the CS8416 S/PDIF Re- ceiver, by the CS42L55 supplied with a master clock, or via an CS8416 Digital Audio Receiver I/O stake header with a DSP connected. CS8406 Digital Audio Transmitter RCA connectors are provided for CS42L55 analog inputs and I/O Stake Headers and SMA Connectors HP/Line outputs. A 1/8 inch audio jack is provided for head- External IC Control Port Accessibility phone stereo out. Digital I/O connections are available via RCA phono or optical connectors to the CS8416 and CS8406 External DSP Serial Audio I/O Accessibility (S/PDIF Rx and Tx). Direct DSP Serial Audio I/O accessibility with CS42L55 through SMA connectors The CDB42L55 is programmed via the PCs USB using Cirrus Logics Microsoft Windows -based FlexGUI software. The Multiple Power Supply options via USB, Battery evaluation board may also be configured to accept external or External Power Supplies timing and data signals for operation in a user application dur- ing system development. 1.65 V to 3.3 V Logic Interface FlexGUI S/W Control - Windows Compatible Ordering Information Pre-defined & User-configurable Scripts CDB42L55 Evaluation Board CODEC Power PC Control Board Power External 5.0 V LDOs Supply 1.8 V Serial 1.8 V x3 2.5 V VL, VCP, VLDO, VA Buck AAA Alkaline MUX 3.3 V 3.3 V (VL only) (not included) LDO USB IC for all applicable 24 MHz devices Oscillator Stereo Circuit Break for PLL Input 1 External System Interface FPGA CS42L55 S/PDIF Rx Clock/Data Routing PCM Stereo Clocks/Data Input 2 Clock dividers and PLL used to derive all applicable Fs from 24 MHz oscillator IC Clocks/ S/PDIF Tx Data Tri-state Buffers SRC (Tx) SRC (Rx) Stereo HP Stereo Line HP Output Output I/O SMA Connectors Jack I/O Stake Headers for Audio for External System Precisions Programmable Serial Interface Interface Adapter (PSIA) Copyright Cirrus Logic, Inc. 2008 DEC 08 (All Rights Reserved) CDB42L55 TABLE OF CONTENTS 1. QUICK START GUIDE ........................................................................................................................... 4 2. SYSTEM OVERVIEW ............................................................................................................................. 5 2.1 Control Port and Board Configuration .............................................................................................. 5 2.2 Power ............................................................................................................................................... 5 2.3 Digital Input ....................................................................................................................................... 5 2.3.1 CS8416 S/PDIF Digital Audio Receiver .................................................................................. 5 2.3.2 CS8421 Sample Rate Converter (Tx SRC to CS42L55) ......................................................... 6 2.4 Digital Output .................................................................................................................................... 6 2.4.1 CS8406 S/PDIF Digital Audio Transmitter .............................................................................. 6 2.4.2 CS8421 Sample Rate Converter (Rx SRC from CS42L55) ....................................................6 2.5 FPGA ................................................................................................................................................ 6 2.6 Oscillator ........................................................................................................................................... 7 2.7 CS42L55 Audio CODEC .................................................................................................................. 7 3. CONFIGURATION OPTIONS ................................................................................................................. 8 3.1 S/PDIF or PSIA In to Analog Out ...................................................................................................... 8 3.2 Analog In to S/PDIF or PSIA Out ...................................................................................................... 9 4. SOFTWARE MODE CONTROL......................................................................................................... 10 4.1 Board Configuration Tab ................................................................................................................ 11 4.2 CODEC Configuration Tab ............................................................................................................. 12 4.3 Analog Input Volume Tab ............................................................................................................... 13 4.4 DSP Engine Tab ............................................................................................................................. 14 4.5 Analog Output Volume Tab ............................................................................................................ 15 4.6 Register Maps Tab ......................................................................................................................... 16 5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 17 6. PERFORMANCE PLOTS ..................................................................................................................... 19 7. CDB42L55 BLOCK DIAGRAM ............................................................................................................ 24 8. CDB42L55 SCHEMATICS ................................................................................................................... 25 9. CDB42L55 LAYOUT ............................................................................................................................ 30 10. REVISION HISTORY .......................................................................................................................... 35 2 DS773DB1