CDB8422 Cirrus Logic

CDB8422 Evaluation Board for CS8422 Features Description Using the CDB8422 evaluation board is an ideal way to IEC-60958, AES3/EBU, S/PDIF Inputs evaluate the CS8422. Use of the board requires a digital Single-Ended Inputs via Optical and RCA signal source, an analyzer, and a power supply. A Win- Input Jacks dows PC-compatible computer is also required if using Differential Inputs via XLR Input Jack software mode to configure the CDB8422. S/PDIF and AES3/EBU input connections are made via S/PDIF Outputs RCA phono, optical, or XLR connectors to the CS8422. Optical and RCA Output Jacks S/PDIF output connections are made via RCA phono or CS8406 Digital Audio Transmitter optical connectors from the CS8406 (S/PDIF Tx). Sys- tem timing can be provided by a S/PDIF or AES3/EBU I/O Stake Headers input signal, by the CS8422 with supplied master clock, External Control Port Accessibility or by an I/O stake header with a DSP connected. External Serial Audio I/O Accessibility The provided Windows-based software GUI makes configuring the CDB8422 easy. The software communi- 3.3 V Logic Interface cates through the PCs USB port to configure the board so that all features of the CS8422 can be evaluated. Powered by Single External Power Supply or The board may also be configured without a PC con- PC USB Port Connection nection by using hardware switches however, not all configurations of the CDB8422 are possible in hard- H/W Control via DIP Switches ware mode. FlexGUI S/W Control - Windows Compatible ORDERING INFORMATION Pre-Defined & User-Configurable Scripts CDB8422 Evaluation Board Crystal Canned Oscillator Oscillator Canned Reset XTI RMCK Jumper Mux Oscillator OMCK OSCLK1 ISCLK CS8406 TX Output ISCLK OLRCK1 ILRCK ILRCK SDOUT1 SDIN SDIN CS8422 OSCLK2 RX Input OLRCK2 SDOUT2 TDM IN USB Micro- 2 USB I C/SPI controller Resistors FPGA Hardware Reset Switches Copyright Cirrus Logic, Inc. 2010 MAY 10 (All Rights Reserved) CDB8422 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1.2 Grounding and Power Supply Decoupling ....................................................................................... 4 1.3 FPGA ............................................................................................................................................... 4 1.4 CS8422 ............................................................................................................................................ 4 1.5 CS8406 Digital Audio Transmitter .................................................................................................... 5 1.6 CS8422 XTI Sources ....................................................................................................................... 5 1.7 I/O Stake Headers ........................................................................................................................... 5 1.8 S/PDIF and AES3/EBU Inputs ......................................................................................................... 5 2. SOFTWARE MODE ................................................................................................................................ 6 2.1 Quick Start Guide ............................................................................................................................. 6 2.2 Configuration Options ...................................................................................................................... 7 2.2.1 S/PDIF In to S/PDIF and PCM Out ......................................................................................... 7 2.2.2 AES3/EBU In to S/PDIF and PCM Out ................................................................................... 8 2.2.3 PCM In to S/PDIF and PCM Out .............................................................................................9 2.2.4 TDM In to TDM Out ............................................................................................................... 10 2.3 Software Mode Control .................................................................................................................. 11 2.3.1 CS8422 Main Setup Tab ....................................................................................................... 12 2.3.2 CS8422 Receiver Controls and Status Tab .......................................................................... 13 2.3.3 CS8422 Interrupt Controls and Status Tab ........................................................................... 14 2.3.4 FPGA Controls Tab ............................................................................................................... 15 2.3.5 Register Maps Tab ................................................................................................................ 16 2.4 FPGA Register Quick Reference ................................................................................................... 17 2.5 FPGA Register Descriptions .......................................................................................................... 17 2.5.1 Code Revision ID (Address 01h) - Read Only ....................................................................... 17 2.5.2 MCLK Control (Address 02h) ................................................................................................ 17 2.5.2.1 SAO2 HDR MCLK Source (SAO2 Mclk) ................................................................... 17 2.5.2.2 SAO1 HDR and CS8406 MCLK Source (SAO1 Mclk) .............................................. 17 2.5.2.3 AUX MCLK Source (AUX Mclk) ................................................................................ 18 2.5.2.4 CS8422 Reset Pin (DUT RST) ................................................................................. 18 2.5.3 Subclock Control (Address 03h) ............................................................................................ 18 2.5.3.1 TDM Header Subclock Source (TDM SEL) ..............................................................18 2.5.3.2 SAI Subclock Source (SAI MS) ................................................................................ 18 2.5.3.3 SAO2 Subclock Source (SAO2 MS) ......................................................................... 19 2.5.3.4 SAO1 Subclock Source (SAO1 MS) ......................................................................... 19 2.5.4 CS8406 Control 1 (Address 04h) .......................................................................................... 19 2.5.4.1 OMCK/ILRCK Ratio (HWCK) ..................................................................................... 19 2.5.4.2 Validity Bit (VBIT IN) .................................................................................................19 2.5.4.3 User Data (UBIT IN) ................................................................................................. 20 2.5.4.4 TCBL (TCBL) ............................................................................................................. 20 2.5.4.5 C BIT (CBIT INT) ...................................................................................................... 20 2.5.4.6 Interface Format (SFMT) ........................................................................................... 20 2.5.5 CS8406 Control 2 (Address 05h) .......................................................................................... 21 2.5.5.1 CS8406 Reset Pin (8406 RST) ................................................................................. 21 2.5.5.2 AUDIO Bit (AUDIOb) ................................................................................................. 21 3. HARDWARE MODE ............................................................................................................................. 22 3.1 Quick Start Guide ........................................................................................................................... 22 3.2 Configuration Options .................................................................................................................... 23 3.2.1 AES3/EBU In to S/PDIF and PCM Out ................................................................................. 23 3.2.2 TDM In to TDM Out ............................................................................................................... 24 3.3 Hardware Mode Control ................................................................................................................. 25 4. SYSTEM CONNECTIONS ................................................................................................................... 28 2 DS692DB2