CRD5381 Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design Features Analog Performance System Features Advanced Multi-bit Delta-sigma Architecture Output Sample Rate Determined by Input Word, Left/Right, or Fsync Clock 24-bit Conversion No External Master Clock Required 120 dB Dynamic Range Easily Scalable for Additional Channels -110 dB THD+N Sample Rates from 27 kHz to 192 kHz Performance insensitivity to Input Clock Jitter Four-Channel Time-Division Multiplexed Output Digital Filter Characteristics Two Independent Stereo, Left-Justified 125 dB Stop-band Rejection Outputs Phase-Matched Outputs CS5381 A CS8421 A LEFT SDOUT SDIN SDOUT Quad Speed Master Input RIGHT Slave Mode Slave Ouput 2 2 TDM ENABLE Differential Analog Inputs 1-4 SDOUT A PCM Data Ouput/ Serial Clock Input Header, J4 TDM/SDOUT B 2 2 LRCK INPUT SCLK INPUT TDM IN LEFT CS5381 B CS8421 B SDOUT SDIN SDOUT Quad Speed Master Input RIGHT Slave Mode Slave Output Copyright Cirrus Logic, Inc. 2005 MAY 05 (All Rights Reserved) CRD5381 Description The combination of the CS5381 Analog-to-Digital Converter and CS8421 Asynchronous Sample Rate Converter creates an analog-to-digital conversion system with an asynchronous digital decimation filter that is virtually immune to interface or network jitter. In addition, the CS8421 adds a multi-channel Time Division Multiplexed (TDM) output format option. These unique features address many of the issues and design challenges associated with networked audio systems and other high-performance applications. In addition to the standard 24-bit audio data, the CS8421 adds the functionality to output properly dithered 32, 20, or 16-bit data. The CRD5381 was designed as a platform for easy evaluation of the jitter rejection, sample rate conversion, and time-division multiplexing capabilities of the CS8421 in the context of a A/D conversion system with an asynchro- nous decimation filter. The CRD5381 accepts four channels of balanced, analog audio input and provides four channels of PCM data output. The data output can be either a four-channel TDM format or two independent stereo left-justified data outputs. The PCM data output is synchronous to the serial left-right clock and bit clock that the user supplies. The CRD5381 also provides status indicators including ADC overflow and SRC unlock, and it accepts an external reset signal. The only system power requirements for the design include +/- 12 Volts and +3.3 Volts. The required input signals are a left/right or word clock and serial clock for the audio data output. This document includes operational instructions and schematics for the CRD5381 and is a companion document to the Cirrus Logic applications note AN270, Audio A/D conversion with Asynchronous Decimation Filter 1 . Please also refer to the CS5381 and CS8421 data sheets for specific product information and specifications 2,3 . Both doc- uments, as well as AN270, are available online at