CS4354 5-V Stereo DAC with 2-V Ground-Centered Output RMS Features Description Advanced multibit deltasigma modulator The CS4354 is a complete stereo digital-to-analog sys- tem including digital interpolation, third-order multi-bit 101 dB A-weighted dynamic range deltasigma digital-to-analog conversion, digital de-em- 86 dB THD+N phasis, analog filtering, and on-chip 2 V line-level RMS driver from a 5 V supply. Single-ended ground-centered analog architecture The advantages of this architecture include ideal differ- No DC-blocking capacitors required ential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tem- Integrated inverting charge pump perature, high tolerance to clock jitter, and a minimal set Filtered line-level outputs of external components. 2V full-scale output RMS These features are ideal for cost-sensitive, two-channel Low-latency digital filtering audio systems including video game consoles, Blu-Ray Supports sample rates up to 192 kHz Disc and DVD players, set-top boxes, digital TVs, and DAB/DMB devices. 24-bit IS input +5-V analog supply with integrated inverting The CS4354 is available in a 14-pin SOIC package in charge pump and regulator for core logic, and Commercial (40C to +85C) grade. The CDB4354 +1.8-V to +5-V interface power supplies Customer Demonstration Board is also available for de- vice evaluation and implementation suggestions. 50-mW power consumption Please see Ordering Information on page 23 for com- 14-pin SOIC, lead-free assembly plete details. Interface Supply (VL) Analog Supply (VA) +1.8V to +5V +5 V 1.8V reg Inverting Charge Pump Power-On Reset -VA Ground-Centered, 2 Vrms Line Level Outputs Left Channel PCM Serial Interpolation Multibit IS Serial DAC Filters + HPF Modulator Audio Port Audio Input Right Channel Auto Speed Mode Detect Copyright Cirrus Logic, Inc. 2014 OCT 14 (All Rights Reserved) CS4354 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ........................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 RECOMMENDED OPERATING CONDITIONS .................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5 DAC ANALOG CHARACTERISTICS .................................................................................................... 6 COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICS ................................... 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ......................................................... 8 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 10 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 10 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 11 2.1 Digital I/O Pin Characteristics ........................................................................................................ 11 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 4. APPLICATIONS ................................................................................................................................... 13 4.1 Ground-Centered Line Outputs ...................................................................................................... 13 4.2 Sample Rate Range/Operational Mode Detect .............................................................................. 13 4.3 System Clocking ............................................................................................................................ 13 4.4 Serial Clock .................................................................................................................................... 14 4.4.1 External Serial Clock Mode ................................................................................................... 14 4.4.2 Internal Serial Clock Mode .................................................................................................... 14 4.4.2.1 De-Emphasis Control ................................................................................................. 14 4.5 Internal High-Pass Filter ................................................................................................................ 15 4.6 Digital Interface Format .................................................................................................................. 15 4.7 Internal Power-On Reset ............................................................................................................... 15 4.8 Initialization .................................................................................................................................... 16 4.9 Recommended Operational Sequences ........................................................................................ 18 4.9.1 Power-Up .............................................................................................................................. 18 4.9.2 Power-Down .......................................................................................................................... 18 4.9.3 Sample Rate Change ............................................................................................................ 18 4.10 Grounding and Power Supply Arrangements ..............................................................................18 4.10.1 Capacitor Placement ........................................................................................................... 19 5. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS .............................. 20 6. PARAMETER DEFINITIONS ................................................................................................................ 22 7. PACKAGE INFORMATION .................................................................................................................. 23 7.1 Dimensions .................................................................................................................................... 23 7.2 Thermal Characteristics ................................................................................................................. 23 8. ORDERING INFORMATION ................................................................................................................ 23 9. REVISION HISTORY ............................................................................................................................ 24 LIST OF FIGURES Figure 1. External Serial Clock Mode Input Timing ..................................................................................... 9 Figure 2. Internal Serial Clock Mode Input Timing ...................................................................................... 9 Figure 3. Internal Serial Clock Generation .................................................................................................. 9 Figure 4. Power-On Reset Threshold Sequence ...................................................................................... 10 Figure 5. Typical Connection Diagram ...................................................................................................... 12 Figure 6. CS4354 Data Format (IS) ......................................................................................................... 14 Figure 7. De-Emphasis Curve, Fs = 44.1 kHz .......................................................................................... 15 Figure 8. Internal Power-On Reset Circuit ................................................................................................ 15 Figure 9. Initialization and Power-Down Sequence Diagram .................................................................... 17 Figure 10. Single-Speed Stopband Rejection ........................................................................................... 20 Figure 11. Single-Speed Transition Band ................................................................................................. 20 Figure 12. Single-Speed Transition Band (detail) ..................................................................................... 20 Figure 13. Single-Speed Passband Ripple ............................................................................................... 20 2 DS895F3