CS5345 104 dB, 24-Bit, 192 kHz Stereo Audio ADC A/D Features General Description Multi-Bit Delta Sigma Modulator The CS5345 integrates an analog multiplexer, program- mable gain amplifier, and stereo audio analog-to-digital 104 dB Dynamic Range converter. The CS5345 performs stereo analog-to-digi- -95 dB THD+N tal (A/D) conversion of up to 24-bit serial values at Stereo 6:1 Input Multiplexer sample rates up to 192 kHz. Programmable Gain Amplifier (PGA) A 6:1 stereo input multiplexer is included for selecting 12 dB Gain, 0.5 dB Step Size between line-level and microphone-level inputs. The Zero Crossing, Click-Free Transitions microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is avail- Stereo Microphone Inputs able for line or microphone inputs and provides +32 dB Gain Stage gain/attenuation of 12 dB in 0.5 dB steps. Low-Noise Bias Supply The output of the PGA is followed by an advanced 5th- Up to 192 kHz Sampling Rates order, multi-bit delta sigma modulator and digital filter- Selectable Serial Audio Interface Formats ing/decimation. Sampled data is transmitted by the Left-Justified up to 24-bit serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode. IS up to 24-bit High-Pass Filter or DC Offset Calibration Integrated level translators allow easy interfacing be- tween the CS5345 and other devices operating over a System Features wide range of logic levels. Power-Down Mode The CS5345 is available in a 48-pin LQFP package in Commercial (-10 to +70 C) grade. The CDB5345 Cus- +3.3 V to +5 V Analog Power Supply, Nominal tomer Demonstration board is also available for device +3.3 V to +5 V Digital Power Supply, Nominal evaluation and implementation suggestions. Please re- Direct Interface with 1.8 V to 5 V Logic Levels fer to Ordering Information on page 42 for complete details. Pin-Compatible with CS4245 1.8 V to 5 V 3.3 V to 5 V 3.3 V to 5 V IC/SPI Left PGA Output Internal Voltage Control Data Right PGA Output Register Configuration Reference Interrupt Stereo Input 1 Stereo Input 2 Overflow Stereo Input 3 High Pass Low-Latency Multibit Reset Oversampling PGA Filter Anti-Alias Filter ADC +32 dB MUX Stereo Input 4 / Mic Input 1 & 2 Multibit Serial +32 dB High Pass Low-Latency PGA Oversampling Audio Filter Anti-Alias Filter ADC Output Stereo Input 5 Stereo Input 6 Copyright Cirrus Logic, Inc. 2012 AUG 12 (All Rights Reserved) DS658F4 CS5345 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ......................................................................................................................... 5 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 SPECIFIED OPERATING CONDITIONS ............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS .......................................................................................................7 ADC ANALOG CHARACTERISTICS ................................................................................................... 8 ADC ANALOG CHARACTERISTICS ................................................................................................. 10 ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 11 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13 PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15 DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 20 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 21 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22 4. APPLICATIONS ................................................................................................................................... 23 4.1 Recommended Power-Up Sequence ............................................................................................. 23 4.2 System Clocking ............................................................................................................................. 23 4.2.1 Master Clock ......................................................................................................................... 23 4.2.2 Master Mode ......................................................................................................................... 24 4.2.3 Slave Mode ........................................................................................................................... 24 4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 24 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................26 4.5 Input Connections ........................................................................................................................... 26 4.6 PGA Auxiliary Analog Output ......................................................................................................... 26 4.7 Control Port Description and Timing ............................................................................................... 27 4.7.1 SPI Mode ............................................................................................................................... 27 4.7.2 IC Mode ................................................................................................................................ 27 4.8 Interrupts and Overflow .................................................................................................................. 29 4.9 Reset .............................................................................................................................................. 29 4.10 Synchronization of Multiple Devices ............................................................................................. 29 4.11 Grounding and Power Supply Decoupling .................................................................................... 29 5. REGISTER QUICK REFERENCE ........................................................................................................ 31 6. REGISTER DESCRIPTION .................................................................................................................. 32 6.1 Chip ID - Register 01h .................................................................................................................... 32 6.2 Power Control - Address 02h ......................................................................................................... 32 6.2.1 Freeze (Bit 7) ......................................................................................................................... 32 6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 32 6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 32 6.2.4 Power-Down Device (Bit 0) ................................................................................................... 32 6.3 ADC Control - Address 04h ............................................................................................................ 33 6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 33 6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 33 6.3.3 Mute (Bit 2) ............................................................................................................................ 33 6.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 33 6.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 33 6.4 MCLK Frequency - Address 05h .................................................................................................... 34 6.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 34 6.5 PGAOut Control - Address 06h ...................................................................................................... 34 6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 34 6.6 Channel B PGA Control - Address 07h .......................................................................................... 34 2 DS658F4