CS8427 96 kHz Digital Audio Interface Transceiver Features General Description The CS8427 is a stereo digital audio transceiver with Complete EIAJ CP1201, IEC-60958, AES3, AES3 and serial digital audio inputs, AES3 and serial S/PDIF-compatible Transceiver digital audio outputs, and includes comprehensive con- trol ability through a 4-wire microcontroller port. Channel +5.0 V Analog Supply (VA+) status and user data are assembled in block-sized buff- +3.3 V or +5.0 V Digital Interface (VL+) ers, making read/modify/write cycles easy. Flexible 3-wire Serial Digital I/O Ports A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Adjustable Sample Rate up to 96 kHz Target applications include A/V receivers, CD-R, DVD Low-jitter Clock Recovery receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- Pin and Microcontroller Read/Write Access to tomotive audio systems. Channel Status and User Data The CS8427 is available in 28-pin SOIC and TSSOP Microcontroller and Standalone Modes packages in Commercial (-10C to +70C) and Automo- Differential Cable Driver and Receiver tive (-40C to +85C) grades. The CDB8427 Customer Demonstration Board is also available for device evalu- On-chip Channel Status and User Data Buffer ation and implementation suggestions. Please see Memories Permit Block Reads & Writes Ordering Information on page 49 for complete details. OMCK System Clock Mode Decodes Audio CD Q Sub-code I VL+ DGND VA+ AGND FILT RERR RMCK ILRCK OLRCK Serial Serial ISCLK OSCLK Audio Audio SDIN Input Output SDOUT RXP TXP Clock & AES3 C& U bit AES3 Receiver Driver Data S/PDIF Data S/PDIF RXN Recovery Decoder Buffer Encoder TXN Control Output Misc. Port & Clock Control Registers Generator H/S RST EMPH U TCBL SDA/ SCL/ AD1/ AD0/ INT OMCK CDOUT CCLK CDIN CS MAY 10 Copyright Cirrus Logic, Inc. 2010 www.cirrus.com (All Rights Reserved) DS477F5 1CS8427 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5 SPECIFIED OPERATING CONDITIONS ................................................................................. 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 DC ELECTRICAL CHARACTERISTICS................................................................................... 6 DIGITAL INPUT CHARACTERISTICS ..................................................................................... 6 DIGITAL INTERFACE SPECIFICATIONS................................................................................ 6 TRANSMITTER CHARACTERISTICS ..................................................................................... 6 SWITCHING CHARACTERISTICS .......................................................................................... 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 8 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 9 SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE..................................... 10 2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 11 3. GENERAL DESCRIPTION ..................................................................................................... 12 3.1 Audio Input/Output Ports ................................................................................................. 12 3.2 Serial Control Port ............................................................................................................ 12 3.3 Channel Status and User bit Memory .............................................................................. 12 3.4 AES3 and S/PDIF Standards Documents ........................................................................ 13 4. DATA I/O FLOW AND CLOCKING OPTIONS ....................................................................... 13 5. THREE-WIRE SERIAL AUDIO PORTS ................................................................................. 15 6. AES3 RECEIVER .................................................................................................................... 16 6.1 OMCK System Clock Mode ............................................................................................. 16 6.2 PLL, Jitter Attenuation, and Varispeed ............................................................................ 16 6.3 Error Reporting and Hold Function .................................................................................. 16 6.4 Channel Status Data Handling ......................................................................................... 16 6.5 User Data Handling .......................................................................................................... 17 6.6 Non-Audio Auto Detection ............................................................................................... 17 7. AES3 TRANSMITTER ........................................................................................................... 18 7.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 18 7.2 TXN and TXP Drivers ...................................................................................................... 18 8. MONO MODE OPERATION ................................................................................................... 19 8.1 Receiver Mono Mode ....................................................................................................... 19 8.2 Transmitter Mono Mode ................................................................................................... 19 9. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 25 9.1 SPITM Mode .................................................................................................................... 25 9.2 IC Mode .......................................................................................................................... 25 9.3 Interrupts .......................................................................................................................... 25 10. CONTROL PORT REGISTER SUMMARY ........................................................................... 27 10.1 Memory Address Pointer (MAP) ..................................................................................... 27 11. CONTROL PORT REGISTER BIT DEFINITIONS ................................................................ 28 11.1 Control 1 (01h)................................................................................................................ 28 11.2 Control 2 (02h)................................................................................................................ 28 11.3 Data Flow Control (03h).................................................................................................. 29 11.4 Clock Source Control (04h)............................................................................................. 30 11.5 Serial Audio Input Port Data Format (05h)...................................................................... 31 11.6 Serial Audio Output Port Data Format (06h)................................................................... 31 11.7 Interrupt 1 Status (07h) (Read Only)............................................................................... 32 11.8 Interrupt 2 Status (08h) (Read Only)............................................................................... 33 11.9 Interrupt 1 Mask (09h).....................................................................................................33 11.10 Interrupt 1 Mode MSB (0Ah) & Interrupt 1 Mode LSB (0Bh)......................................... 33 11.11 Interrupt 2 Mask (0Ch).................................................................................................. 34 11.12 Interrupt 2 Mode MSB (0Dh) & Interrupt 2 Mode LSB (0Eh) ........................................ 34 11.13 Receiver Channel Status (0Fh) (Read Only) ................................................................ 34 2 DS477F5