WM8199 w 20MSPS 16-bit CCD Digitiser DESCRIPTION FEATURES 16-bit ADC The WM8199 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals 20MSPS conversion rate from CCD sensors or Contact Image Sensors (CIS) at pixel 30MSPS conversion rate at 8-bits sample rates of up to 20MSPS. Low power 358mW typical The device includes three analogue signal processing 5V single supply or 5V/3.3V dual supply operation channels each of which contains Reset Level Clamping, Single or 3 channel operation Correlated Double Sampling and Programmable Gain and Correlated double sampling Offset adjust functions. Three multiplexers allow single Programmable gain (8-bit resolution) channel processing. The output from each of these Programmable offset adjust (8-bit resolution) channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is Programmable clamp voltage available in 8 or 4-bit wide multiplexed format. 8 or 4-bit wide multiplexed data output formats Internally generated voltage references An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS 28-lead SSOP package signals or during Reset Level Clamping to clamp CCD Serial control interface signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum APPLICATIONS performance from the device. Flatbed and sheetfeed scanners Using an analogue supply voltage of 5V and a digital USB compatible scanners interface supply of either 5V or 3.3V, the WM8199 typically Multi-function peripherals only consumes 358mW when operating from a single 5V supply. High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB w CL R V TIMING CONTROL WM8199 S S VREF/BIAS R 8 M OFFSET OEB G U DAC X B RINP RLC CDS + PGA + M U I/P SIGNAL R 8 M OP 0 X POLARITY G U OP 1 ADJUST X B OP 2 DATA OP 3 I/O M 16- OP 4 GINP RLC CDS BIT PORT + PGA + U OP 5 X ADC 8 OFFSET OP 6 8 I/P SIGNAL DAC OP 7 /SDO POLARITY ADJUST BINP RLC CDS + PGA + 8 OFFSET 8 I/P SIGNAL DAC POLARITY CONFIGURABLE SEN ADJUST SERIAL SCK CONTROL SDI RLC 4 INTERFACE RLC/ACYC DAC AGND1 AGND2 DGND WOLFSON MICROELECTRONICS plc Production Data, July 2008, Rev 4.4 To receive regular email updates, sign up at WM8199 Production Data TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TYPICAL HIGH SPEED PERFORMANCE..................................................................... 8 INPUT VIDEO SAMPLING............................................................................................. 9 OUTPUT DATA TIMING ................................................................................................ 9 SERIAL INTERFACE ................................................................................................... 10 INTERNAL POWER ON RESET CIRCUIT ..........................................................12 DEVICE DESCRIPTION.......................................................................................14 INTRODUCTION.......................................................................................................... 14 INPUT SAMPLING....................................................................................................... 14 RESET LEVEL CLAMPING (RLC) ............................................................................... 14 CDS/NON-CDS PROCESSING ................................................................................... 15 OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 16 ADC INPUT BLACK LEVEL ADJUST .......................................................................... 16 OVERALL SIGNAL FLOW SUMMARY ........................................................................ 17 CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 17 OUTPUT FORMATS.................................................................................................... 18 CONTROL INTERFACE .............................................................................................. 19 TIMING REQUIREMENTS........................................................................................... 19 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 20 REFERENCES............................................................................................................. 20 POWER SUPPLY ........................................................................................................ 20 POWER MANAGEMENT ............................................................................................. 21 LINE-BY-LINE OPERATION ........................................................................................ 21 OPERATING MODES.................................................................................................. 22 OPERATING MODE TIMING DIAGRAMS ................................................................... 23 DEVICE CONFIGURATION .................................................................................26 REGISTER MAP .......................................................................................................... 26 REGISTER MAP DESCRIPTION................................................................................. 27 RECOMMENDED EXTERNAL COMPONENTS ..................................................30 PACKAGE DIMENSIONS ....................................................................................31 IMPORTANT NOTICE ..........................................................................................32 ADDRESS:................................................................................................................... 32 PD, Rev 4.4, July 2008 w 2