WM8234GEFL/V Cirrus Logic

WM8234 135 MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES 135 MSPS conversion rate The WM8234 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals 16 bit ADC resolution from CCD sensors or Contact Image Sensors (CIS) at pixel Current consumption 280mA sample rates of up to 22.5 MSPS per channel. 3.3V single supply operation The device has six analogue signal processing channels Sample and hold / correlated double sampling each of which contains Reset Level Clamping, Correlated Programmable offset adjust (8-bit resolution) Double Sampling (also Sample and Hold), Programmable Flexible clamp timing Gain, Automatic Gain Control (AGC) and Offset adjust Pixel clamp / line clamp mode functions. Programmable clamp voltage The output from each of these channels is time multiplexed, Programmable CIS/CCD timing generator in pairs, into two high-speed 16-bit Analogue to Digital Internally generated voltage references Converters. The digital data is available in a variety of Compliant for Spread Spectrum Clock output formats via the flexible data port. LVDS/CMOS output options The WM8234 has a user selectable LVDS or CMOS output LVDS 5-pair 315 MHz 35-bit data architecture. CMOS 90 MHz output maximum An internal 5-bit DAC is supplied for internal reference level Complete on chip clock generator. MCLK 5 22.5 MHz generation. This may be used during CDS to reference CIS Internal timing adjustment signals or during clamping to clamp CCD signals. An Automatic Gain Control external reference level may also be supplied. ADC references are generated internally, ensuring optimum Automatic Black Level Calibration performance from the device. 56-lead QFN package 7mm x 7mm Serial control interface A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data. The WM8234 features a sensor timing clock generator for APPLICATIONS both CCD and CIS sensors. The clock generator can accept a slow or fast reference clock input and also has a flexible Digital copiers timing adjustment function for output timing clocks to allow USB2.0 compatible scanners use of many different sensors. Multi-function peripherals High-speed CCD/CIS sensor interface Rev 4.8 Copyright Cirrus Logic, Inc., 2010 2018 NOV 18 WM8234 BLOCK DIAGRAM VRLC/VBIAS AVDD2 AVDD1 VREF1C VREF2C VREF3C DBVDD VREF /BIAS WM8234 CDS IN1 + PGA + RLC S/H I/P SIGNAL OFFSET POLARITY DAC ADJUST D 10/16 CDS M 16bit I + PGA + + IN2 RLC U S/H ADC G HZCTRL OFFSET X I I/P SIGNAL DAC T POLARITY A ADJUST L CDS 7 IN3 + + RLC PGA D1P/OP 0 S/H C D1N/OP 1 I/P SIGNAL OFFSET O POLARITY 7 DAC D2P/OP 2 N ADJUST D2N/OP 3 T LVDS( 7 R D3P/OP 4 Chanel CDS IN4 + + RLC PGA O D3N/OP 5 link)/ S/H 7 I/P SIGNAL L D4P/OP 6 OFFSET CMOS POLARITY DAC D4N/OP 7 ADJUST & 7 D5P/OP 8 M 10/16 D5N/OP 9 CDS 16bit + IN5 RLC + PGA + U D S/H 7 ADC DCLKP/OC 1 X A OFFSET DCLKN/OC 2 I/P SIGNAL T DAC POLARITY A ADJUST M CDS + PGA IN6 RLC + A S/H P OFFSET I/P SIGNAL P DAC POLARITY I ADJUST N LDO1VDD LDO1GND LDO1 G LDO1VOUT BLACK LEVEL LDO2VDD CALIBRATION LDO2GND LDO2 LDO2VOUT RLC AUTO GAIN DAC Phase CONTROL MCLK Adjustment SDO CCD SENSOR SEN SERIAL TIMING GENERATION CONTROL SCK INTERFACE SDI AGND3 AGND2 AGND1 MON DSLCT1 DSLCT2 DBGND 2 Rev 4.8 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 TGSYNC