WM8235
210MSPS 9-Channel AFE with Sensor
Timing Generation and LVDS/CMOS Data Output
DESCRIPTION FEATURES
210MSPS conversion rate
The WM8235 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals 16-bit ADC resolution
from CCD sensors or Contact Image Sensors (CIS) at pixel
Current consumption 390mA
sample rates of up to 23MSPS per channel.
3.3V single supply operation
The device has nine analogue signal processing channels Sample and hold / correlated double sampling
each of which contains Reset Level Clamping, Correlated
Programmable offset adjust (8-bit resolution)
Double Sampling (also Sample and Hold), Programmable
Flexible clamp timing
Gain, Automatic Gain Control (AGC) and Offset adjust
Pixel clamp / line clamp mode
functions.
Programmable clamp voltage
The output from each of these channels is time multiplexed,
Programmable CIS/CCD timing generator
in pairs, into three high-speed 16-bit Analogue to Digital
Internally generated voltage references
Converters. The digital data is available in a variety of
Compliant for Spread Spectrum Clock
output formats via the flexible data port.
LVDS/CMOS output options
The WM8235 has a user selectable LVDS or CMOS output
LVDS 5pair 490MHz 35-bit data
architecture.
CMOS 90MHz output maximum
An internal 5-bit DAC is supplied for internal reference level
Complete on chip clock generator. MCLK 5MHz to 23MHz
generation. This may be used during CDS to reference CIS
Internal timing adjustment
signals or during clamping to clamp CCD signals. An
Automatic Gain Control
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum Automatic Black Level Calibration
performance from the device.
56-lead QFN package 7mm x 7mm
Serial control interface
A programmable automatic Black-Level Calibration function
is available to adjust the DC offset of the output data.
The WM8235 features a sensor timing clock generator for
APPLICATIONS
both CCD and CIS sensors. The clock generator can accept
a slow or fast reference clock input and also has a flexible
Digital copiers
timing adjustment function for output timing clocks to allow
USB2.0 compatible scanners
use of many different sensors.
Multi-function peripherals
High-speed CCD/CIS sensor interface
Rev 4.5
Copyright Cirrus Logic, Inc., 20102015
DEC 15
WM8235
BLOCK DIAGRAM
VRLC/VBIAS
VREF1C VREF2C VREF3C DBVDD
AVDD1 AGND1
VREF
/BIAS
CDS
IN1
+ PGA +
RLC
S/H
WM8235
I/P SIGNAL
OFFSET
POLARITY
DAC
ADJUST
M
10/16
CDS 16bit
IN2 U +
RLC + PGA +
S/H ADC
X
OFFSET HZCTRL
I/P SIGNAL
DAC
D
POLARITY
I
ADJUST
G
I
CDS
IN3
RLC + PGA +
T
S/H
OFFSET A
I/P SIGNAL
DAC
L
POLARITY
D1P/OP[0]
ADJUST
C
D1N/OP[1]
7
O
CDS
IN4 D2P/OP[2]
RLC + PGA +
N
S/H D2N/OP[3]
I/P SIGNAL
OFFSET T
7 LVDS(
POLARITY
DAC D3P/OP[4]
R Chanel
ADJUST D3N/OP[5]
O
link)/
7
D4P/OP[6]
M L
CMOS
10/16
CDS 16bit
IN5
+ PGA + U +
RLC D4N/OP[7]
S/H ADC
7
X
&
D5P/OP[8]
OFFSET
I/P SIGNAL
D5N/OP[9]
DAC
POLARITY D 7
DCLKP/OC[1]
ADJUST
A
DCLKN/OC[2]
T
CDS 7
IN6
RLC + PGA +
A
S/H
OFFSET
I/P SIGNAL M
DAC
POLARITY
A
ADJUST
P
P
CDS
IN7
+ PGA + I
RLC
S/H
N
I/P SIGNAL
OFFSET
G
POLARITY
DAC
ADJUST 10/16
16bit
+
M
ADC
CDS
IN8
RLC + PGA + U
S/H
X
OFFSET
I/P SIGNAL
DAC LDO1VDD
POLARITY LDO1GND
LDO1
ADJUST LDO1VOUT
CDS
IN9
RLC + PGA +
LDO2VDD
S/H
LDO2 LDO2GND
OFFSET
LDO2VOUT
I/P SIGNAL
DAC
POLARITY
ADJUST
BLACK LEVEL
CALIBRATION
RLC
DAC
Phase
AUTO GAIN
MCLK
Adjustment
CONTROL
SDO
CCD SENSOR SEN
SERIAL
TIMING GENERATION CONTROL SCK
INTERFACE SDI
MON DSLCT1 DSLCT2 DBGND
2 Rev 4.5
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
TGSYNC