CMX138AE1 CML Microcircuits

CMX138A CML Microcircuits Audio Scrambler and COMMUNICATION SEMICONDUCTORS Sub-Audio Signalling Processor D/138A/4 October 2014 CMX138A: Audio Scrambler and Sub-Audio Signalling Processor with Auxiliary System Clock, ADC and DAC for use in Analogue Radio Systems Features Programmable Audio Scrambler Selectable Audio Processing Order Concurrent Audio/Signalling Operations Sub-audio Signalling: CTCSS, DCS Auxiliary System Clock Output Full Audio-band Processing: Pre and De-emphasis, Compandor, Tx Output for Single-point Modulation Scrambler and Selectable 2.55/3 kHz Filters Low-power (3.0V to 3.6V) Operation Auxiliary ADC and Auxiliary DAC Flexible Powersave Modes C-BUS Serial Interface to Host Controller Available in 28-pin TSSOP Package Two Analogue Inputs (Mic or Discriminator) DAC Output ADC Input 3.0V to 3.6V Modulator Discriminator CMX138A Audio Scrambler RF and C-BUS Sub-Audio Processor Host GPIO Built on FirmASIC technology C System Clock 1 Reference Clock 1 Brief Description The CMX138A is a half-duplex, audio scrambler and sub-audio signalling processor IC for Analogue Two- way Radio applications. This makes it a suitable device for the leisure radio markets (FRS, MURS, PMR446 and GMRS). This device provides a user programmable frequency inversion audio scrambler, companding and pre/de- emphasis performing simultaneous processing of Sub-audio and In-band signalling. Other features include an auxiliary ADC channel and an auxiliary DAC interface (with optional RAMDAC, to facilitate transmitter power ramping). The device has flexible powersaving modes and is available in a 28-pin (E1) TSSOP package. 2014 CML Microsystems Plc Audio Scrambler and Sub-Audio Signalling Processor CMX138A CONTENTS Section Page 1 Brief Description ...................................................................................................................... 1 2 History ...................................................................................................................................... 5 3 Block Diagram .......................................................................................................................... 6 4 Signal List ................................................................................................................................. 7 4.1 Signal Definitions .......................................................................................................... 8 5 External Components.............................................................................................................. 9 5.1 PCB Layout Guidelines and Power Supply Decoupling .............................................. 11 6 General Description ............................................................................................................... 12 7 Detailed Descriptions ............................................................................................................ 13 7.1 Xtal Frequency ............................................................................................................ 13 7.2 Host Interface ............................................................................................................. 13 7.2.1 C-BUS Operation ................................................................................................. 13 7.3 Device Control ............................................................................................................ 15 7.3.1 Signal Routing ...................................................................................................... 15 7.3.2 Mode Control ........................................................................................................ 16 7.4 Audio Functions .......................................................................................................... 17 7.4.1 Audio Receive Mode ............................................................................................ 17 7.4.2 Audio Transmit Mode ........................................................................................... 19 7.4.3 Audio Compandor ................................................................................................ 23 7.5 Sub-audio Signalling ................................................................................................... 25 7.5.1 Receiving and Decoding CTCSS Tones .............................................................. 27 7.5.2 Receiving and Decoding DCS Codes .................................................................. 28 7.5.3 Transmit CTCSS Tone ......................................................................................... 30 7.5.4 Transmit DCS Code ............................................................................................. 30 7.6 In-band Signalling User Tones ................................................................................ 30 7.6.1 Receiving and Decoding In-band Tone ................................................................ 30 7.6.2 Transmitting In-band Tone ................................................................................... 31 7.7 Auxiliary ADC Operation ............................................................................................. 31 7.8 Auxiliary DAC/RAMDAC Operation ............................................................................ 32 7.9 Digital System Clock Generator.................................................................................. 33 7.9.1 Main Clock Operation ........................................................................................... 33 7.9.2 System Clock Operation ...................................................................................... 33 7.10 GPIO ........................................................................................................................... 34 7.11 Signal Level Optimisation ........................................................................................... 34 7.11.1 Transmit Path Levels ........................................................................................... 34 7.11.2 Receive Path Levels............................................................................................. 34 8 C-BUS Register Summary ..................................................................................................... 35 8.1.1 Interrupt Operation ............................................................................................... 36 8.1.2 General Notes ...................................................................................................... 36 9 Configuration Guide .............................................................................................................. 37 2014 CML Microsystems Plc Page 2 D/138A/4