CML Microcircuits CMX148 PMR Audio and Data Processor COMMUNICATION SEMICONDUCTORS D/148/6 November 2010 Audio Processing, DTMF and FFSK/MSK Data Modem with Auxiliary Functions for use in Analogue PMR Systems Features Concurrent Audio/Signalling/Data Operations Dual Auxiliary ADC, 4 Multiplexed Inputs 4 x Auxiliary DACs Complete Audio-band Processing: o Selectable Audio Processing Order Dual Programmable System Clock Outputs o Pre and De-emphasis Tx Outputs for Single, Two-Point or I/Q o Selectable 2.55/3.0 kHz Filtering Modulation o Selectable Audio HPF Cut-off Microphone and Discriminator Analogue o Compandor Inputs o Limiter Programmable Voice Scrambler Digital Gain Adjustment MSK/FFSK Data Modem with Packet or Free- Default 3.6864MHz Xtal/Clock format Modes with FEC, CRC, Interleaving and C-BUS Serial Interface to Host Controller Scrambling DTMF and Audio Tone Encoder/Decoder Flexible Powersave Modes Routing to Support Host Controller Signalling Low-power 3.3V Operation Sub-Audio Signalling Filters for CTCSS and DCS Small VQFN and LQFP Packages Auxiliary Audio Out Multiplexed ADC Inputs Mic Input Auxiliary Filtered Signal for Host Decoding DACs Host Generated Signalling CMX148 Modulator PMR Voice and Data Processor IRQ Discriminator Host C RF C-BUS Tx Enable Rx Enable Reference Clock System Clock 1 3.3V Supply System Clock 2 1. Brief Description The CMX148 is a half-duplex, audio, signalling and data processing IC for use in PMR systems that utilise the host C to perform signalling, including CTCSS/DCS encoding/decoding. The device is intended for use in general leisure and professional PMR terminals. Comprehensive audio processing facilities include complete audio processing, filtering, companding, pre- or de-emphasis and frequency inversion scrambling. The CMX148 features an FFSK/MSK data modem for packetised or free-format data operations. Signal routing and filtering is included to assist host C based signal encoding/decoding applications. A DTMF encoder/decoder, a full complement of auxiliary ADCs and DACs and dual synthesised clock outputs are included in this low power PMR processor. The device also has flexible powersaving modes and is available in 48-pin VQFN and LQFP packages. 2010 CML Microsystems Plc PMR Audio and Data Processor CMX148 CONTENTS Section Page 1. Brief Description.....................................................................................................................1 1.1. History..........................................................................................................................5 2. Block Diagram ........................................................................................................................6 3. Signal List................................................................................................................................7 4. External Components ............................................................................................................9 5. PCB Layout Guidelines and Power Supply Decoupling...................................................11 6. General Description .............................................................................................................12 7. Detailed Descriptions...........................................................................................................13 7.1. Device Identification Code.........................................................................................13 7.2. Xtal Frequency ..........................................................................................................13 7.3. Host Interface ............................................................................................................13 7.4. Device Control...........................................................................................................15 7.4.1. Signal Routing.....................................................................................................15 7.4.2. Mode Control ......................................................................................................16 7.5. Audio Functions.........................................................................................................17 7.5.1. Audio Receive Mode...........................................................................................17 7.5.2. Audio Transmit Mode..........................................................................................20 7.6. External Sub-Audio Signalling...................................................................................26 7.7. Inband Signalling.......................................................................................................26 7.7.1. Receiving DTMF Tones ......................................................................................27 7.7.2. Transmitting DTMF Tones ..................................................................................27 7.7.3. Transmitting Audio Tones...................................................................................27 7.8. MSK/FFSK Data Modem...........................................................................................27 7.8.1. Receiving MSK/FFSK Signals ............................................................................28 7.8.2. Transmitting MSK/FFSK Signals ........................................................................28 7.9. MSK/FFSK Data Packetising ....................................................................................29 7.9.1. Tx Hang Bit .........................................................................................................29 7.9.2. Frame Format .....................................................................................................29 7.9.3. Frame Head ........................................................................................................29 7.9.4. Data Block Coding ..............................................................................................30 7.9.5. CRC and FEC Encoding Information..................................................................31 7.9.6. Data Interleaving.................................................................................................31 7.9.7. Data Scrambling/Privacy Coding ........................................................................31 7.9.8. Data Buffer Timing ..............................................................................................32 7.10. Auxiliary ADC Operation ...........................................................................................32 7.11. Auxiliary DAC/RAMDAC Operation...........................................................................33 7.12. Digital System Clock Generator ................................................................................34 7.12.1. Main Clock Operation .........................................................................................35 7.12.2. System Clock Operation .....................................................................................35 7.13. GPIO..........................................................................................................................35 7.14. Signal Level Optimisation..........................................................................................35 7.14.1. Transmit Path Levels ..........................................................................................35 2010 CML Microsystems Plc 2 D/148/6