CMX910 AIS Baseband Processor D/910/6 March 2009 Provisional Issue Features: Half-Duplex GM(F)SK, FSK and DSC Capabilities I and Q Radio Interface Slot/Sample Counter with UTC Timing Interface Low-Power (3.0 to 3.6V) Operation Optimum Co-channel and Adjacent-channel Low Profile, 64-lead LQFP (L9) and Performance Leadless VQFN (Q1) Packages Flexible Signal Channels Auxiliary ADC and DAC Functions Two Simultaneous Rx 5 x (10-bit) DACs One Tx 5-Input MUX (10-bit) ADC Optional FSK Interface AIS Data Formatted and Raw Data Modes Applications: Supports Carrier-Sensing Channel Access Automatic Identification System (CSTDMA) Operation (AIS) for Marine Safety RF Device-Enable Facilities Class A or B AIS Transponders C-BUS Serial Interface with Expansion Port AIS Rx-only Modules Aux Aux CMX910 ADC DACs Radio Rx1: I/Q GMSK/ HDLC/ Message down- FSK NRZI ADCs buffers C-BUS converter decoder decoder Host C Interface Tx: I/Q GMSK/ HDLC/ Message RF up- FSK NRZI DACs buffer converter encoder encoder Other C-BUS C-BUS Rx2: I/Q GMSK/ HDLC/ Expansion Message Port down- FSK NRZI Devices ADCs buffers converter decoder decoder Optional GNSS FSK Device FSK Reset and Slot and Demod. Interrupt Engine Enable Retiming Power Sample (FX604) Generator Port (External) Control Timer TCXO 1. Brief Description A highly integrated Baseband Signalling Processor IC, the CMX910 fulfils the requirements of the class A and class B marine Automatic Identification System (AIS) transponder market. The CMX910 is half duplex in operation, comprising two parallel I+Q Rx paths and one Tx path. These are configurable for AIS or DSC operation. The device performs channel filtering and signal modulation/demodulation with associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing (flags, bit stuffing/de-stuffing, CRC generate/check). An external 1200bps FSK demodulator interface provides a third parallel decode path for DSC, as required by the class A market. Integrated Rx/Tx data buffers and a flexible slot/sample timer are also provided, all of which greatly reduce the processing requirements of the host C. Provision of a C-BUS expansion port, an RF device enable port and a number of auxiliary ADCs and DACs further simplifies the system hardware design, reducing the overall equipment cost and size. 2009 CML Microsystems Plc AIS Baseband Processor CMX910 CONTENTS Section Page 1. Brief Description .................................................................................................1 2. Block Diagram .....................................................................................................4 3. Signal List ............................................................................................................5 4. External Components.........................................................................................7 5. General Description............................................................................................8 5.1 Overview of CMX910 Operation............................................................8 5.2 C-BUS Interface......................................................................................9 5.3 Reset and Power Control ....................................................................12 5.3.1 RESETN pin .............................................................................12 5.3.2 General Reset Command .......................................................12 5.3.3 Clock Control...........................................................................12 5.4 Slot and Sample Timer ........................................................................13 5.4.1 Manual Nudge..........................................................................16 5.4.2 Auto Nudge..............................................................................17 5.4.3 Sleep Mode ..............................................................................17 5.4.4 Selecting the Nudge Trigger Value ......................................18 5.5 Transmit Operation..............................................................................19 5.5.1 Transmitter Registers.............................................................19 5.5.2 AIS Raw Mode Transmit.........................................................24 5.5.3 AIS Burst Mode Transmit .......................................................25 5.5.4 DSC Transmit ..........................................................................27 5.5.5 Transmitter Timing Control....................................................29 5.6 Receive Operation................................................................................32 5.6.1 Receiver Registers..................................................................33 5.6.2 AIS Raw Mode Receive...........................................................37 5.6.3 AIS Burst Mode Receive.........................................................38 5.6.4 DSC Receive (Main Channel).................................................39 5.6.5 DSC Receive (External FSK Interface)..................................39 5.7 Auxiliary A-to-D Converter..................................................................40 5.8 Auxiliary D-to-A Converters................................................................42 5.9 Interrupt Generator ..............................................................................46 5.10 Device Enable Port...............................................................................48 5.11 C-BUS Expansion Port ........................................................................49 5.12 Special Command Interface................................................................50 6. Supplementary Information .............................................................................52 6.1 Glossary of Terms................................................................................52 7. Performance Specification...............................................................................54 7.1 Electrical Performance ........................................................................54 7.1.1 Absolute Maximum Ratings...................................................54 7.1.2 Operating Limits......................................................................54 7.1.3 Operating Characteristics......................................................55 7.2 Packaging .............................................................................................60 2009 CML Microsystems Plc 2 D/910/6