DAVICOM Semiconductor, Inc. DM9161B 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DATA SHEET Final Version: DM9161B-DS-F01 October 16, 2009 1 Final Version: DM9161B-DS-F01 October 16, 2009 DM9161B 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Table of Contents 1. General Description...................................................................3 8.1 Basic Mode Control Register (BMCR) - 00............................24 8.2 Basic Mode Status Register (BMSR) - 01 .............................25 2. Features ....................................................................................3 8.3 PHY ID Identifier Register 1 (PHYIDR1) - 02 ......................26 8.4 PHY ID Identifier Register 2 (PHYIDR2) - 03 ......................26 3. Block Diagram ...........................................................................4 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 ......................................................................................27 4. Pin Configuration:......................................................................5 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 0528 8.7 Auto-negotiation Expansion Register (ANER) 5. Pin Description ..........................................................................6 - 06 ......................................................................................29 5.1 Normal MII Interface, 21 pins ..................................................6 8.8 DAVICOM Specified Configuration Register (DSCR) 16.....29 5.2 Media Interface, 4 pins ............................................................8 8.9 DAVICOM Specified Configuration and Status Register 5.3 LED Interface, 3 pins...............................................................8 (DSCSR) - 17 ......................................................................31 5.4 Mode, 2 pins............................................................................8 8.10 10Base-T Configuration / Status (10BTCSR) - 18...............32 5.5 Bias and Clock, 4 pins.............................................................9 8.11 DAVICOM Specified Interrupt Register - 21 ........................32 5.6 Power, 13 pins.........................................................................9 8.12 DAVICOM Specified Receive Error Counter Register (RECR) - 5.7 Table of Media Type Selection................................................9 22.........................................................................................33 5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI 8.13 DAVICOM Specified Disconnect Counter Register (DISCR) - (7-Wired) Mode .................................................................. 10 23.........................................................................................33 8.14 DAVICOM Hardware Reset Latch State 6. LED Configuration ...................................................................11 Register (RLSR) - 24 ............................................................34 6.1 LED Functional Description....12 8.17 Power Saving Control Register (PSCR) 29 ......................34 9. DC and AC Electrical Characteristics 7. Functional Description.............................................................13 9.1 Absolute Maximum Ratings (25C).........................................35 7.1 MII interface...........................................................................13 9.2 Operating Conditions.............................................................35 7.2 100Base-TX Operation..........................................................15 9.3 DC Electrical Characteristics .................................................36 7.2.1 100Base-TX Transmit.........................................................15 9.4 AC Electrical Characteristics & Timing 7.2.1.1 4B5B Encoder .................................................................16 Waveform .............................................................................. 36 7.2.1.2 Scrambler .....................................................................16 9.4.1 TP Interface ........................................................................36 7.2.1.3 Parallel to Serial Converter..............................................16 9.4.2 Oscillator/Crystal Timing.....................................................36 7.2.1.4 NRZ to NRZI Encoder .....................................................16 9.4.3 Power On Reset Timing......................................................37 7.2.1.5 MLT-3 Converter .............................................................16 9.4.4 MDC/MDIO Timing .............................................................37 7.2.1.6 MLT-3 Driver....................................................................16 9.4.5 MDIO Timing when OUTPUT by STA ................................37 7.2.1.7 4B5B Code Group ...........................................................17 9.4.6 MDIO Timing when OUTPUT by DM9161B .......................37 7.2.2 100Base-TX Receiver ........................................................18 9.4.7 100Base-TX Transmit Timing Parameters .........................38 7.2.2.1 Signal Detect ...................................................................18 9.4.8 100Base-TX Transmit Timing Diagram ..............................38 7.2.2.2 Adaptive Equalizer...........................................................18 9.4.9 100Base-TX Receive Timing Parameters ..........................38 7.2.2.3 MLT-3 to NRZI Decoder ..................................................18 9.4.10 MII 100Base-TX Receive Timing Diagram .......................39 7.2.2.4 Clock Recovery Module...................................................18 7.2.2.5 NRZI to NRZ....................................................................18 7.2.2.6 Serial to Parallel ..............................................................18 9.4.11 MII 10Base-T Nibble Transmit Timing Parameters ..........39 7.2.2.7 Descrambler ....................................................................18 9.4.12 MII 10Base-T Nibble Transmit Timing 7.2.2.8 Code Group Alignment....................................................18 Diagram..........................................................................39 7.2.2.9 4B5B Decoder .................................................................18 9.4.13 MII 10Base-T Receive Nibble Timing Parameters .......... 40 7.2.3 10Base-T Operation ...........................................................18 9.4.14 MII 10Base-T Receive Nibble Timing 7.2.4 Collision Detection..............................................................19 Diagram..........................................................................40 7.2.5 Carrier Sense .....................................................................19 9.4.15 Auto-negotiation and Fast Link Pulse Timing Parameters40 7.2.6 Auto-Negotiation.................................................................19 9.4.16 Auto-negotiation and Fast Link Pulse Timing Diagram ....41 7.2.7 MII Serial Management ......................................................20 9.4.17 RMII Receive Timing Diagram..........................................41 7.2.8 Serial Management Interface .............................................20 9.4.18 RMII Transmit Timing Diagram.........................................41 9.4.19 RMII Timing Diagram........................................................42 7.2.9 Management Interface Read Frame Structure..............................................................................20 9.4.20 RMII Timing Parameter ....................................................42 7.2.10 Management Interface Write Frame Structure ..............20 7.2.11 Power Reduced Mode......................................................21 9.4.21 Magnetics Selection Guide43 7.2.12 Power Down Mode ...........................................................21 7.2.13 Reduced Transmit Power Mode.......................................21 10. Package Information..............................................................44 7.2.14 Feedback Vout and Vin for 5V..21 7.3 HP Auto-MDIX Functional Description..........................................22 11. Order Information...................................................................45 8. MII Register Description ..........................................................23 Final 2 Version: DM9161B-12-DS-F01 October 16, 2009