DM9161 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver 1. General Description The DM9161 is a physical layer, single-chip, and low functions of 100BASE-TX as defined by IEEE802.3u, power transceiver for 100BASE-TX 100BASE-FX and including the Physical Coding Sublayer (PCS), 10BASE-T operations. On the media side, it provides Physical Medium Attachment (PMA), Twisted Pair a direct interface either to Unshielded Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), Category 5 Cable (UTP5) for 100BASE-TX Fast 10BASE-TX Encoder/Decoder (ENC/DEC), and Ethernet, or UTP5/UTP3 Cable for 10BASE-T Twisted Pair Media Access Unit (TPMAU). The Ethernet. Through the Media Independent Interface DM9161 provides a strong support for the (MII), the DM9161 connects to the Medium Access auto-negotiation function, utilizing automatic media Control (MAC) layer, ensuring a high inter-operability speed and protocol selection. Furthermore, due to the from different vendors. built-in wave-shaping filter, the DM9161 needs no external filter to transport signals to the media in The DM9161 uses a low power and high performance 100BASE-TX or 10BASE-T Ethernet operation. CMOS process. It contains the entire physical layer 2. Block Diagram 100Base-FX PECL Interface 100Base- MII/RMII/ TX 100Base-TX GPSI PCS Transceiver Interface 10Base-T TX/RX Module LED Driver Auto-Negotiation Clock Biasing/ MII MII Circuit Power Management Register Control Block Block Final 1 Version: DM9161-DS-F05 September 10, 2008 DM9161 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver Table of Contents 1. General Description.............................................. 3 7.2.13 Reduced Transmit Power Mode.................. 20 2. Block Diagram ...................................................... 3 3. Features ............................................................... 4 8. MII Register Description ..................................... 21 4. Pin Configuration: DM9161 LQFP........................ 5 8.1 Basic Mode Control Register (BMCR) - 00 ...... 22 8.2 Basic Mode Status Register (BMSR) - 01........ 23 5. Pin Description ..................................................... 6 8.3 PHY ID Identifier Register 1 (PHYIDR1) - 02. 24 5.1 Normal MII Interface, 21 pins ............................. 6 8.4 PHY ID Identifier Register 2 (PHYIDR2) - 03. 24 5.2 Media Interface, 4 pins....................................... 8 8.5 Auto-negotiation Advertisement Register (ANAR) 5.3 LED Interface, 3 pins.......................................... 8 - 04................................................................... 25 5.4 Mode, 2 pins....................................................... 8 8.6 Auto-negotiation Link Partner Ability Register 5.5 Bias and Clock, 4 pins........................................ 9 (ANLPAR) - 05................................................. 26 5.6 Power, 13 pins.................................................... 9 8.7 Auto-negotiation Expansion Register (ANER) 5.7 Table A ............................................................... 9 - 06................................................................... 27 5.8 Pin Maps of Normal MII, Reduced MII, and 8.8 DAVICOM Specified Configuration Register 10Base-T GPSI (7-Wired) Mode..................... 10 (DSCR) 16 ......................................................27 8.9 DAVICOM Specified Configuration and Status 6. LED Configuration.............................................. 11 Register (DSCSR) - 17 .................................... 29 8.10 10Base-T Configuration / Status (10BTCSR) - 18 7. Functional Description........................................ 12 ......................................................................... 30 7.1 MII interface...................................................... 12 8.11 DAVICOM Specified Interrupt Register - 21... 30 7.2 100Base-TX Operation..................................... 14 8.12 DAVICOM Specified Receive Error Counter 7.2.1 100Base-TX Transmit ................................... 14 Register (RECR) - 22....................................... 31 7.2.1.1 4B5B Encoder ............................................ 15 8.13 DAVICOM Specified Disconnect Counter 7.2.1.2 Scrambler .................................................15 Register (DISCR) - 23...................................... 31 7.2.1.3 Parallel to Serial Converter ........................ 15 8.14 DAVICOM Hardware Reset Latch State 7.2.1.4 NRZ to NRZI Encoder ................................ 15 Register (RLSR) - 24....................................... 31 7.2.1.5 MLT-3 Converter ........................................ 15 7.2.1.6 MLT-3 Driver .............................................. 15 9. DC and AC Electrical Characteristics 7.2.1.7 4B5B Code Group...................................... 16 9.1 Absolute Maximum Ratings( 25C ) .................. 32 7.2.2 100Base-TX Receiver ................................... 17 9.2 Operating Conditions........................................ 32 7.2.2.1 Signal Detect .............................................. 17 9.3 DC Electrical Characteristics............................ 33 7.2.2.2 Adaptive Equalizer ..................................... 17 9.4 AC Electrical Characteristics & Timing 7.2.2.3 MLT-3 to NRZI Decoder............................. 17 Waveform .......................................................... 33 7.2.2.4 Clock Recovery Module ............................. 18 9.4.1 TP Interface................................................... 33 7.2.2.5 NRZI to NRZ............................................... 18 9.4.2 Oscillator/Crystal Timing ............................... 33 7.2.2.6 Serial to Parallel ......................................... 18 9.4.3 MDC/MDIO Timing ........................................ 34 7.2.2.7 Descrambler ............................................... 18 9.4.4 MDIO Timing when OUTPUT by STA........... 34 7.2.2.8 Code Group Alignment............................... 18 9.4.5 MDIO Timing when OUTPUT by DM9161 .... 34 7.2.2.9 4B5B Decoder............................................ 18 9.4.6 100Base-TX Transmit Timing Parameters.... 35 7.2.3 10Base-T Operation...................................... 18 9.4.7 100Base-TX Transmit Timing Diagram......... 35 7.2.4 Collision Detection......................................... 18 9.4.8 100Base-TX Receive Timing Parameters..... 35 7.2.5 Carrier Sense ................................................ 18 9.4.9 MII 100Base-TX Receive Timing Diagram.... 36 7.2.6 Auto-Negotiation............................................ 18 9.4.10 MII 10Base-T Nibble Transmit Timing 7.2.7 MII Serial Management ................................. 19 Parameters.................................................. 36 7.2.8 Serial Management Interface ........................ 19 9.4.11 MII 10Base-T Nibble Transmit Timing 7.2.9 Management Interface Read Frame Diagram ....................................................... 36 Structure......................................................... 19 9.4.12 MII 10Base-T Receive Nibble Timing 7.2.10 Management Interface Write Frame Structure Parameters.................................................. 37 ...................................................................... 19 9.4.13 MII 10Base-T Receive Nibble Timing 7.2.11 Power Reduced Mode................................. 20 Diagram ....................................................... 37 7.2.12 Power Down Mode...................................... 20 2 Final Version: DM9161-DS-F05 September 10, 2008