AT45DB321D
32Mb, 2.5V or 2.7V
DataFlash
DATASHEET
(NOT RECOMMENDED FOR NEW DESIGNS. USE AT45DB321E.)
Features
Single 2.5V - 3.6V or 2.7V - 3.6V supply
RapidS serial interface: 66MHz maximum clock frequency
SPI compatible modes 0 and 3
User configurable page size
512 bytes per page
528 bytes per page
Page size can be factory preconfigured for 512 bytes
Page program operation
Intelligent programming operation
8,192 pages (512/528 bytes/page) main memory
Flexible erase options
Page erase (512 bytes)
Block erase (4KB)
Sector erase (64KB)
Chip erase (32Mb)
Two SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the flash array
Continuous read capability through entire array
Ideal for code shadowing applications
Low power dissipation
7mA active read current ,typical
25 A standby current, typical
15 A deep power down, typical
Hardware and software data protection features
Individual sector
Sector lockdown for secure code and data storage
Individual sector
Security: 128-byte security register
64-byte user programmable space
Unique 64-byte device identifier
JEDEC standard manufacturer and device ID read
100,000 program/erase cycles per page, minimum
Data retention: 20 years
Industrial temperature range
Green (Pb/halide-free/RoHS compliant) packaging options
3597TDFLASH11/20131. Description
The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital
voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for
applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz.
The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory,
the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a
page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically
erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained,
three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple
address lines and a parallel interface, DataFlash devices use a RapidS serial interface to sequentially access its data. The
simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,
minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial
applications where high density, low pin count, low voltage and low power are essential.
To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
All programming and erase cycles are self timed.
Figure 1-1. Pin configurations and pinouts.
(1)
MLF (VDFN) SOIC
Top View Top View
SI 1 8 SO
SI 1 8 SO
2 7
SCK GND
SCK 2 7 GND
3 6
RESET VCC
RESET 3 6 VCC
4 5
CS WP
CS 4 5 WP
Note: 1. The metal pad on the bottom of
the MLF package is floating.
This pad can be a No Connect or
connected to GND.
BGA Package Ball-out TSOP: Type 1
Top View Top View
1 2 3 4 5
RDY/BUSY 1 28 NC
RESET 2
27 NC
WP 3 26 NC
NC 4 25 NC
A
NC 5 24 NC
NC NC NC NC
VCC 6 23 NC
B
GND 7 22 NC
NC SCK GND VCC NC
NC 8 21 NC
C
NC 9 20 NC
NC CS RDY/BSY WP NC
NC 10 19 NC
D
CS 11 18 NC
NC SO SI RESET NC
SCK 12 17 NC
E SI 13 16 NC
NC NC NC NC NC
SO 14 15 NC
Note: TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.
AT45DB321D [DATASHEET] 2
3597TDFLASH11/2013