RM24C128DS-LTAI-B Dialog Semiconductor

RM24C128DS 128-Kbit 1.65V Minimum Non-volatile Serial EEPROM 2 I C Bus Advance Datasheet Features Memory array: 128Kbit non-volatile EEPROM serial memory Single supply voltage: 1.65V - 3.6V 2 2-wire I C interface 2 Compatible with I C bus modes: -100kHz -400kHz -1MHz Page size: 64 bytes -Byte and Page Write from 1 to 64 bytes 128-byte, One-Time Programmable (OTP) Security Register - 64 bytes factory programmed with a unique identifier - 64 bytes user programmable Low Energy Byte Write -Byte Write consuming 50 nJ Low power consumption -0.25 mA active Read current -1.0 mA active Write current -1.0 A Standby current Fast Write -Page Write in 3 ms (64 byte page) -Byte Write within 60 s Random and sequential Read modes Industrys lowest read cycle latency Unlimited read cycles Write protect of the whole memory array 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN and WLCSP packages RoHS-compliant and halogen-free packaging Data Retention: >40 years at 125C Endurance: 100,000 write cycles (for both byte and page write cycles) - No degradation across temperature range No data loss under UV exposure on bare die or WLCSP Based on Adesto s proprietary CBRAM technology Description The Adesto RM24C128DS is a 128Kbit, serial EEPROM memory device that utilizes Adesto s CBRAM resistive technology. The memory devices use a single low- voltage supply ranging from 1.65V to 3.6V. DS-RM24C128DS115B11/20162 2 The Adesto I C device is accessed through a 2-wire I C compatible interface consisting of a Serial Data (SDA) and Serial Clock (SCL). The maximum clock (SCL) frequency is 1MHz. The devices have both byte write and page write capability. Page write is 64 bytes. The Byte Write operation of CBRAM consumes only 10% of the energy consumed by a Byte Write operation of EEPROM devices of similar size. Adesto s EEPROM endurance can be as much as 40X higher than industry standard EEPROM devices operating in byte write mode at 85C. Unlike EEPROMs based on floating gate technology (which require read-modify-write on a whole page for every write operation) CBRAM write endurance is based on the capability to write each byte individually, irrespective of whether the user writes single bytes or an entire page. Additionally, unlike floating gate technology, CBRAM does not experience any degradation of endurance across the full temperature range. By contrast, in order to modify a single byte, most EEPROMs modify and write full pages of 32, 64 or 128 bytes. This provides significantly less endurance for floating gate devices used in byte write mode when compared to page write mode. The Page Write operation of CBRAM is 4-6 times faster than the Page Write operation of similar EEPROM devices. Both random and sequential reads are available. Sequential reads are capable of reading the entire memory in one operation. External address pins permit up to eight devices on the same data bus. The devices are available in standard 8-pin SOIC, TSSOP and 8-pad UDFN. RM24C128DS 2 DS-RM24C128DS115B11/2016