JTAG HS1 JTAG HS1 Programming Cable for Xilinx FPGAs Programming Cable for Xilinx FPGAs Revision: June 10, 2011 1300 Henley Court Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The JTAG-HS1 programming cable is a high- speed programming solution for Xilinx FPGAs. It is fully compatible will all Xilinx tools, and can be seamlessly driven from iMPACT, Chipscope, and EDK. The HS-1 attaches to target boards using Digilents 6-pin, 100-mil spaced programming header, or Xilinxs 2x7, 2mm connector (using the included adaptor). The JTAG-HS1 is powered from a PCs USB port, and will be recognized as a Digilent programming cable when connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to Small, complete, all-in-one JTAG programming supply JTAG signal buffers. The high speed, solution for Xilinx FPGAs 24mA, three-state buffers allow target boards to Separate Vref drives JTAG/SPI signal voltages drive the HS1 with signal voltages from 1.8V to Vref can be any voltage between 1.8V and 5V. 5V, with bus speeds of up to 30MBit/sec. The High-Speed USB2 port that can drive JTAG/SPI HS1s Vdd pin must be tied to the same voltage bus at up to 30Mbit/sec supply that drives the JTAG port on the FPGA. JTAG/SPI frequency settable by user Compatible with all Xilinx tools JTAG signals are held in high-impedance except when actively driven during programming, so the Uses micro-AB USB2 connector JTAG bus can be shared with other devices. The SPI programming solution (modes 0 and 2 HS1 uses a standard Type-A to Micro-USB supported) cable (included with the HS1) that attaches to Fully supported by the Adept SDK, allowing the end of the module opposite the system custom JTAG/SPI applications to be created board connector. The HS1 is small and light, allowing it to be held firmly in place by the system Micro-USB board connector. V : 5V to 1.8V IO VDD VIO Included Adaptor GND GND USB2 TCK TCK Port TDO TDO TDI TDI 1 2 3 4 5 6 TMS TMS Digilent JTAG Header Xilinx JTAG Header JTAG-HS1 FPGA Single row, 100-mil, 6-pin Dual row, 2-mm, 14-pin Doc: 502-205 page 1 of 3 Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. JTAG HS1 Reference Manual Software Support In addition to working seamlessly with all Xilinx tools, the HS1 is supported by Digilents Adept software and the Adept SDK (the SDK can be freely downloaded from Digilents website). Adept includes a full-featured programming environment, and a set of public APIs that allow user applications to directly drive the JTAG chain. Using the Adept SDK, custom applications can be created to drive JTAG ports on virtually any device. The HS1 also supports SPI modes 0 and 2. By using the APIs provided by the SDK applications can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information. The HS1 is also supported by Digilents AVR programmer that can target any AVR device. Absolute Maximum Ratings Symbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.0 V Vref I/O reference/supply voltage -0.3 6 V VIO Signal Voltage -0.3 6 V -50 VIO < -0.3V TMS, TCK, TDI, TDO I ,I mA IK OK DC Input/Output Diode Current VIO > 6V +20 I DC Output Current 50 mA OUT T Storage Temperature -20 +120 C STG Human Body Model JESD22-A114 2000 V ESD Charge Device Model JESD22-C101 500 V Doc: 502-205 page 2 of 3