1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-HS3 Programming Cable for Xilinx FPGAs Revised March 13, 2019 This manual applies to the JTAG-HS3 rev. A Overview The JTAG-HS3 programming cable is a high-speed programming/debugging solution for Xilinx FPGAs and SoCs. It is fully compatible will all Xilinx Tools, and can be seamlessly driven from iMPACT, ChipScope, EDK, and Vivado. The HS3 attaches to target boards using Xilinxs 2x7, 2mm programming header. The PC powers the JTAG-HS3 through the USB port and will recognize it as a Digilent programming cable when connected, even if the cable is not attached to the target board. The HS3 has a separate Vref pin to supply the JTAG signal buffers. The high speed 24mA three-state buffers allow the HS3 to drive target boards with signal voltages from 1.8V to 5V and bus speeds up to 30MBit/sec (see Fig. 1). To function correctly, the HS3s Vref pin must be tied to the same voltage supply (VCCO 0) that drives the JTAG port on the FPGA. Features include: Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs and SoCs Plugs directly into standard Xilinx JTAG header Separate Vref drives JTAG signal voltages Vref can be any voltage between 1.8V and 5V High-Speed USB2 port that can drive JTAG bus up to 30Mbit/sec (frequency adjustable by user) Compatible with Xilinx ISE 14.1 and newer, Xilinx Vivado 2013.3 and newer Uses micro AB USB2 connector Open drain buffer on pin 14 allows debugging software to reset the processor core of Xilinxs Zynq platform The JTAG-HS3 The JTAG bus can be shared with other devices as the HS3 signals are held in high-impedance, except when actively driven during programming. The HS3 uses a standard Type-A to Micro-USB cable that attaches to the end of the module opposite the system board connector. The HS3 is small and light, allowing it to be held firmly in place by the system board connector (see Fig. 2). V IO : 5 V to 1 .8 V VREF VIO GND GND USB 2 TCK TCK Port TDO TDO TDI TDI TMS TMS JTAG - HS 3 FPGA Figure 1. Diagram of signal voltages and connections. Figure 2. Xilinx JTAG header. Dual row, 2mm, 14 pin. Copyright Digilent, Inc. All rights reserved. DOC : 502-299 Page 1 of 6 Other product and company names mentioned may be trademarks of their respective owners. JTAG-HS3 Reference Manual 1 Software Support The JTAG-HS3 has been designed to work seamlessly with Xilinxs ISE (iMPACT, ChipScope, EDK) and Vivado tool suites. The most recent versions of ISE and Vivado include all of the drivers, libraries, and plugins necessary to communicate with the JTAG-HS3. At the time of writing, the following Xilinx software included support for the HS3: Vivado 2014.1+, Vivado 2013.3+, and ISE 14.1+. The HS3 is also compatible with ISE 13.1 13.4. However, these versions of ISE do not include all of the libraries, drivers, and plugins necessary to communicate with the HS3. In order to use the JTAG-HS3 with these versions of ISE, version 2.5.2 or higher of the Digilent Plugin for Xilinx Tools package must be downloaded from the Digilent website, and the ISE13 plugin must be manually installed as described in the included documentation. The JTAG- HS3 is not compatible with Xilinx Vivado 2013.1 or Vivado 2013.2. In addition to working with the Xilinx Tools, the HS3 is also supported by Digilents Adept software and the Adept SDK (the SDK is available to download free from Digilents website). Adept includes a full-featured programming environment and a set of public APIs that allow user applications to directly drive the JTAG chain. Using the Adept SDK, custom applications can be created to drive JTAG ports on virtually any device. Please see the Adept SDK reference manual for more information. 2 Xilinx Zynq-7000 and SoC Support The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The Zynq platform processor has a pin dedicated for this purpose (PS SRST B). Driving the PS SRST B pin low causes the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of driving this pin low under the instruction of Xilinxs SDK during debugging operations. In order for this to work, pin 14 of Xilinx JTAG header on the target board must be connected to the PS SRST B pin of the Zynq (see Figs. 3 & 4). GND 1 2 VCCO 0 GND 1 2 VREF GND 3 4 TMS GND 3 4 TMS GND 6 TCK GND 6 TCK 5 5 GND 7 8 TDO GND 7 8 TDO GND 9 10 TDI GND 9 10 TDI GND 11 12 ---- GND 11 12 ---- GND 13 14 PS SRST B GND 13 14 SRST Figure 3. JTAG-HS3 pinout (seen looking out of the connector). Figure 4. Xilinx System Board Header (seen looking into the connector). The JTAG-HS3 uses an open drain buffer to drive pin 14 of the Xilinx JTAG header (see Fig. 5). This allows the HS3 to drive the PS SRST B pin when VCC MIO1 is referenced to a different voltage than VCCO 0 (see Fig. 6). Copyright Digilent, Inc. All rights reserved. Page 2 of 6 Other product and company names mentioned may be trademarks of their respective owners.