410-320 Digilent

1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com PmodLVLSHFT Reference Manual Revised April 12, 2016 This manual applies to the PmodLVLSHFT rev. B Overview The Digilent PmodLVLSHFT is a digital logic level shifter. This module is ideal for users who want to supply logic signals following a 3.3V CMOS standard but have an alternate logic level output that is used for other applications such as JTAG programming. Digital logic level shifter Translate logic signals between two user supplied voltage levels 27 JTAG header 8 miniature switches to dictate logic level conversion Voltage range between 1.8V and 5.5V Small PCB size for flexible designs 1.8 in 0.8 in (4.6 cm 2.0 cm) 12-pin Pmod port with GPIO interface The PmodLVLSHFT. 1 Functional Description The PmodLVLSHFT translates logic signals between two user supplied voltage levels. Users can use a small object such as a pen or a screwdriver to adjust the switches for the direction of the voltage translation. 2 Interfacing with the Pmod The PmodLVLSHFT communicates with the host board via GPIO. Users can supply any form of digital signals to either end of the Pmod and have them translated to the other voltage level. Switches are provided to indicate the direction of the voltage translation. A switch pushed to the left side (green) towards the pin header translates voltages from VCCB to VCCA a switch on the right side (yellow) towards the JTAG header translates from VCCA to VCCB. Copyright Digilent, Inc. All rights reserved. DOC : 502-320 Page 1 of 3 Other product and company names mentioned may be trademarks of their respective owners. PmodLVLSHFT Reference Manual Figure 1. Switches indicating the voltage direction. A pinout table for the PmodLVLSHFT is provided below: Header J1 JTAG Header J2 Header J3 Pin Signal Description Pin Signal Description Pin Signal Description A1 & TMS Power Supply B1 & TMS 1 AIO1/TMS 1 GND 1 BIO1/TMS JTAG pin Ground JTAG pin A2 & TDI Power Supply B5 & Signal 2 AIO2/TDI 2 VCCB 2 BIO5/SRST JTAG pin side B Reset pin A3 & TDO Power Supply B2 & TDI 3 AIO3/TDO 3 GND 3 BIO2/TDI JTAG pin Ground JTAG pin A4 & TCK B1 & TMS 4 AIO4/TCK 4 BIO1/TMS 4 BIO6 I/O pin B6 JTAG pin JTAG pin Power Supply Power Supply B3 & TDO 5 GND 5 GND 5 BIO3/TDO Ground Ground JTAG pin Power Supply B4 & TCK 6 VCCA 6 BIO4/TCK 6 BIO7 I/O pin B7 side A JTAG pin Power Supply B4 & TCK 7 AIO5 I/O pin A5 7 GND 7 BIO4/TCK Ground JTAG pin B3 & TDO 8 AIO6 I/O pin A6 8 BIO3/TDO 8 BIO8 I/O pin B8 JTAG pin Power Supply 9 AIO7 I/O pin A7 9 GND Header J4 Ground B2 & TDI 10 AIO8 I/O pin A8 10 BIO2/TDI Pin Signal Description JTAG pin Power Supply Power Supply Power Supply 11 GND 11 GND 1 VCCB Ground Ground side B Power Supply Not Power Supply 12 VCCA 12 (NC) 2 GND side A Connected Ground Power Supply 13 GND Ground 14 SRST Signal Reset Table 1. Pin descriptions for the PmodLVLSHFT. Note* Headers J2 and J3 follow the JTAG pin numbering convention as opposed to the Pmod header numbering convention Copyright Digilent, Inc. All rights reserved. Page 2 of 3 Other product and company names mentioned may be trademarks of their respective owners.