7 GPIO2 GPIO1 6 5 GPIO0 JTAG-SMT2 JTAG-SMT2 PPrrooggrraammmmiinngg MMoodduullee ffoorr XXiilliinnxx FFPPGGAAss Revision: July 25, 2012 1300 Henley Court Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview GND 1 11 Vdd (3.3V) TCK 2 10 GND The Joint Test Action Group (JTAG)-SMT2 is a compact, complete and fully self-contained TDI 3 9 VREF surface-mount programming module for Xilinx TMS 4 8 TDO field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx tools, including iMPACT, Chipscope, and EDK. Users can load the module directly onto a target board and reflow it like any other component. Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs The JTAG-SMT2 uses a 3.3V main power Compatible with all Xilinx tools supply and a separate Vref supply to drive the Compatible with IEEE 1149.7-2009 Class T0 Class JTAG signals. All JTAG signals use high T4 (includes 2-Wire JTAG) speed, 24mA, three-state buffers that allow GPIO pin allows debugging software to reset the signal voltages from 1.8V to 5V and bus processor core of Xilinxs Zynq platform speeds of up to 30MBit/sec. The JTAG bus can Single 3.3V supply be shared with other devices as systems hold JTAG signals at high-impedance, except when Separate Vref drives JTAG signal voltages Vref can actively driven during programming. be any voltage between 1.8V and 5V. The SMT2 module is CE certified and fully High-Speed USB2 port that can drive JTAG/SPI bus compliant with EU RoHS and REACH at up to 30Mbit/sec (frequency settable by user) directives. The module uses a standard Type-A SPI programming solution (modes 0 and 2 up to to Micro-USB cable available for purchase from 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec) Digilent, Inc. Uses micro-AB USB2 connector Users can connect JTAG signals directly to Small form-factor surface-mount module can be the corresponding FPGA signals as shown in directly loaded on target boards Figure 1. For best results, mount the module A similar circuit is available as a stand-alone adjacent to the edge of the host PCB over a programming cable see Digilents JTAG-HS2. ground plane. Although users may run signal Figure 1 traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the 3.3V area immediately beneath the SMT2 clear. V IO 11 Note: Keep the impedance between the Vdd 9 SMT2 and FPGA below 100 Ohms to operate VIO VREF the JTAG at maximum speed. 4 TMS TMS The SMT2 improves upon the SMT1 with the USB2 2 TCK TCK addition of three general purpose IO pins Port 3 (GPIO0 GPIO2) and support for interfacing TDI TDI 8 IEEE 1149.7-2009 JTAG targets in both 2 TDO TDO and 4-wire modes. 1 GND GND JTAG-SMT2 FPGA SMT2 JTAG Port Connections Doc: 502-251 page 1 of 10 JTAG-SMT2 Reference Manual Figure 2 3.3V In addition to supporting JTAG, the JTAG-SMT2 V IO 11 also features two highly configurable Serial Vdd Peripheral Interface (SPI) ports that allow 9 VREF VIO communication with virtually any SPI peripheral. 4 TMS SS (See figure 2) Both SPI ports share the same USB2 2 TCK SCK pins, so users may enable only one port at any Port 3 given time. The table in figure 3 summarizes the TDI MOSI 8 features supported by each port. The HS2 TDO MISO supports SPI modes 0, 1, 2, and 3. 1 GND GND JTAG-SMT2 FPGA SMT2 SPI Port Connections Figure 3 Port SPI Mode Shift Shift Selectable Max SCK Min SCK Inter-byte Number LSB MSB SCK Frequency Frequency Delay First First Frequency 0 Yes Yes Yes 30 MHz 8 KHz 0 1000 S 0 2 Yes Yes Yes 30 MHz 8 KHz 0 1000 S 0 Yes Yes Yes 2.066 MHz 485 KHz 0 1000 S 1 Yes Yes Yes 2.066 MHz 485 KHz 0 1000 S 1 2 Yes Yes Yes 2.066 MHz 485 KHz 0 1000 S 3 Yes Yes Yes 2.066 MHz 485 KHz 0 1000 S Software Support In addition to working seamlessly with all Xilinx tools, Digilents Adept software and the Adept software development kit (SDK) support the SMT2 module. For added convenience customers may freely downloaded the SDK from Digilents website. This Adept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain. With the Adept SDK users can create custom applications that will drive JTAG ports on virtually any device. Users may utilize the APIs provided by the SDK to create applications that can drive any SPI device supporting those modes. Please see the Adept SDK reference manual for more information. IEEE 1149.7-2009 Compatibility The JTAG-HS2 supports several scan formats including the JScan0-JScan3, MScan, and OScan0 - OScan7. It is capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 T4 JTAG Target Systems (TS). (See Figure 4 & 5) Doc: 502-251 page 2 of 10