74AHC138S16-13 Diodes Incorporated

74AHC138 3-TO-8 LINE DECODER DEMULTIPLEXER Description Pin Assignments The 74AHC138 is an advanced high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter. Applications Features Memory chip select decoding Wide Supply Voltage Range from 2.0 V to 5.5 V Demultiplexing Sinks or sources 8mA at Vcc = 4.5V Single line peripheral control CMOS low power consumption Allow simple serial bit streams from a microcontroller to control Schmitt Trigger Action at All Inputs as many peripheral lines as needed. Inputs accept up to 5.5 V ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) Exceeds 1000-V Charged Device Model (C101C) Latch-Up Exceeds 250mA per JESD 78, Class II SO16 Available in Green Molding Compound (no Br, Sb) Lead-Free Finish RoHS Compliant (Notes 1 & 2) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See 74AHC138 Pin Descriptions Pin Number Pin Name Description 1 A0 Address Input 0 2 A1 Address Input 1 3 A2 Address Input 2 4 E1 Enable Input 1 (active LOW) 5 E2 Enable Input 2 (active LOW) 6 E3 Enable Input 3 (active HIGH) 7 Y7 Output 7 (active LOW) 8 GND Ground 9 Y6 Output 6 (active LOW) 10 Y5 Output 5 (active LOW) 11 Y4 Output 4 (active LOW) 12 Y3 Output 3 (active LOW) 13 Y2 Output 2 (active LOW) 14 Y1 Output 1 (active LOW) 15 Y0 Output o (active LOW) 16 V Supply Voltage cc Function Table Diagram Control Input Output E1 E2 E3 A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 H X X X X X H H H H H H H H X H X X X L L L H L L L H H H H H H H L L L H H H H H H H L H L H L H H H H H L H H L H H H H H H L H H H H L L H H H L H H H H H L H H H L H H H H H H H L H L H H H H H H H H H L H H H H H H H 2 of 10 74AHC138 June 2013 Diodes Incorporated www.diodes.com Document number: DS35482 Rev. 2 - 2 Preliminary